PURPOSE: To reduce RAMs and counters in number by transferring pulses to a shift register only when data at a defective part of a bubble memory device is normal, and writing the contents of the shift register in an RAM at every time when a specified number of puses are transferred.

CONSTITUTION: Clock pulse 1 are counted by a counter 2b, whose output is transferred to a selector 12 to select data 6aW6d read out of bubble memory devices 0W3, device by device thereby transferring them to a shift register 13. Only when data of a PROM3 has a level (H) (normal), shift pulses are transferred from a gate 15 to the terminal CK of the shift register 13. When four shift pulses are transferred to the terminal CK of the register 13, the shift register 14 is effected and the output of the shifter register 14 is sent from a gate 7 to the counter 4 and the terminal WE of an RAM5, thereby writing contents QAW QD of the shift register 13 in the RAM5.