PURPOSE: To prevent deterioration of performance of a central processor, by setting a point where the progress of a program is discontinued with an interruption.

CONSTITUTION: The operand value of a debug instruction which is read out of a storage device MS with an instruction address IA of a program status word PSW is set at the 1st storage part S1. At the same time, an operation OP code is decided at an instruction decoding part DEC and then supplied to a comparator part CMP as a control signal. The upper and lower limits of an address range are set as the prescribed value by an external register RG functioning as the 2nd storage part. The part S1 is compared with the register RG at the part CMP. Then the coincidence is obtained to apply an interruption when a program travels within the address range.