PURPOSE: To improve the efficiency of data transfer by temporarily charging a bus connected to the output part of a try/state buffer to logical "1" at the starting ending point of an output period of the try/state buffer.

CONSTITUTION: When a signal *T1 goes to "0", and output of an NAND gate 11 is attained to "1" and an AND gate 3 is turned on, so that a signal SiG1 is inputted to a try/state buffer through the AND gate 3 and outputted to a bus 13. When the signal *T1 rises from "0" to "1", an output TCH of an inverter 10 goes to "1" only for a period corresponding to the delay time of an inverter 8, so that an output of an AND gate 4 is attained to "1" and a pulse signal of logical "1" is sent from the try/state buffer 1 to the bus 13.