Title:
PARALLEL INNER PRODUCT OPERATING METHOD
Document Type and Number:
Japanese Patent JPS60175181
Kind Code:
A
Abstract:
PURPOSE:To find out the inner product of the optional number of data having optional bit length by executing AND operation and total addition by an arithmetic element in which a control register is set up and executing half addition by an arithmetic element in which no control register is set up. CONSTITUTION:The product AB of a multiplicand A and a multiplier B is outputted from the right end of a multiplying circuit 120. To remove the influence of left end inputs d0-d3, f0, only upper 4X4 cells are set up in a register as ''1''. Although a multiplying circuit 121 is a similar circuit as the circuit 120, the circuit 121 finds out the product CD and also outputs the sum AB+CD from the right because the output, i.e. the product AB, of the circuit 120 is sent from the left side. Multiplying circuits 122-123 have similar functions. Consequently, the inner product AB+CD+EF+GH to be found out is outputted from the circuit 123, propagated through residual cells and finally outputted from the lower right of a parallel data processor.
Inventors:
MIYATA HIROYUKI
Application Number:
JP2948684A
Publication Date:
September 09, 1985
Filing Date:
February 21, 1984
Export Citation:
Assignee:
KOGYO GIJUTSUIN
International Classes:
G06F7/53; G06F7/508; G06F7/544; G06F17/16; (IPC1-7): G06F7/52; G06F15/347