Title:
SEMICONDUCTOR CIRCUIT
Document Type and Number:
Japanese Patent JPS5925426
Kind Code:
A
Abstract:
PURPOSE: To realize a high-speed operation and small power consumption, by connecting an enhancement type FET having a clock signal applied to its gate in series to an inverter circuit.
CONSTITUTION: An inverter circuit is provided with a depletion type FETQ5 and an enhancement type FETQ7. An enhancement type FETQ6 having a clock pulse 1 supplied to its gate 17 is provided between the FETQ6 and FETQ7. The inverter circuit generates an output when the FETQ6 conducts by the clock pulse. No current flows to the inverter circuit while the FETQ6 is kept under a nonconductive state, and therefore no electric power is consumed. At the same time, the FETQ6 does not impair the high-speed performance of the inverter circuit.
Inventors:
OKUMURA KOUICHIROU
Application Number:
JP12591883A
Publication Date:
February 09, 1984
Filing Date:
July 11, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K19/096; (IPC1-7): H03K19/096
Domestic Patent References:
| JP45025014A |
Foreign References:
| US3775693A | 1973-11-27 |
Attorney, Agent or Firm:
Uchihara Shin