Title:
SRAM WITH IMPROVED DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS60151890
Kind Code:
A
Abstract:
A static random access memory wherein positive feedback is used in the bit line loads. The output of the first sense amplifier stage is fedback to the gates of depletion-made bit line load transistors, to provide positive feedback during the read or write operation. That is, since one of the complementary bit lines which the accessed memory cell is attempting to pull down sees a load impedance which gradually becomes higher and higher, the memory cell can pull down this bit line more rapidly. To accomplish this with stability, the first sense amplifier stage has less than unity open loop gain, and a succeeding sense amplifier stage is therefore used for further amplification.
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Inventors:
ATSUSHIYUUIN ETSUCHI SHIYAA
Application Number:
JP18163184A
Publication Date:
August 09, 1985
Filing Date:
August 30, 1984
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G11C11/419; G11C11/417; (IPC1-7): G11C11/34
Domestic Patent References:
| JPS5841484A | 1983-03-10 |
Attorney, Agent or Firm:
Hideto Asamura