PURPOSE: To minimize the waiting state period of a device by allowing a channel itself to execute a command sent out of the channel of a CPU to the device through a disk pack controller when the command is not executed normally by the device.

CONSTITUTION: A channel processor 5 includes a processor 6, various register groups 8, and subchannels 7. Each subchannel 7 has a sense information valid bit 10, sense information area 11, and area 12 for the number of sense bytes. Further, a memory 3 has a sense information area 3a, sense valid area 3b, and channel status word 3c. The channel stores information sent from the disk pack controller DPC in the sense information area 11 when an error occurs. Then, the channel itself sends out a sense command to the DPC.