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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS6045059
Kind Code:
A
Abstract:

PURPOSE: To avoid the generation of current leakage even when a contact hole becomes partly off a diffused region by a method wherein only the contact hole on a diffused layer region regarded as having a potential different from that of the peripheral semiconductor layer including the diffused layer region is provided with a poly Si, which is then electrically coupled with a metallic wiring layer.

CONSTITUTION: A poly Si electrode 7 doped with phosphorus, an N type impurity, is grown only on the diffused layer 2 where a potential different from that of the substrate 1 is given, the surface of which electrode is then oxidized, and an the same time phosphorus is diffused to the substrate 1 through the contact hole, thus forming the diffused layer region 2a. Thereby, even when the contact hole becomes partly off the N+ diffused layer 2, a complete P-N including the hole is formed, and the leakage does not generate. Next, after an interlayer insulation film 8 is formed, an aluminum wiring 9 connected to the electrode 7 and an aluminum wiring 10 connected to an N+ diffused layer 3 are formed. Even when the contact hole of the N+ diffused layer 3 becomes off the diffused layer region, the substrate 1 and diffused layer region 3 are not under electric bad influences because of having the same potential. Besides, the electrode 7 and the wiring 10 are insulated by the inter insulation film 8 and do not short-circuit.


Inventors:
FURUTA HIROSHI
Application Number:
JP15270483A
Publication Date:
March 11, 1985
Filing Date:
August 22, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/78; H01L21/28; H01L21/768; H01L23/522; H01L29/43; H01L29/45; (IPC1-7): H01L21/88; H01L29/78
Attorney, Agent or Firm:
Uchihara Shin