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Patent Searching and Data


Title:
MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH04113588
Kind Code:
A
Abstract:

PURPOSE: To start at high speed level, and to improve a write recovery characteristic by providing an nMOS transistor at the source side of an nMOS transistor for driving.

CONSTITUTION: nMOS transistors 1 and 2 are arranged between the source side of nMOS transistors 3 and 4 for driving in push-pull constitution and grounded lines. That is, the drain of the nMOS transistor 1 is connected to the source of the nMOS transistor 3, and the drain of the nMOS transistor 2 is connected to the source of the nMOS transistor 4. And the sources of the nMOS transistors 1 and 2 are connected to the grounded lines, and a ground voltage GND is supplied from the grounded line. A power supply voltage Vcc is supplied to each gate of these nMOS transistors 1 and 2. Thus, the write recovery characteristic is improved, and it is possible to operate at high speed.


Inventors:
SENOO KATSUNORI
Application Number:
JP23052190A
Publication Date:
April 15, 1992
Filing Date:
September 03, 1990
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11C11/417; G11C11/409; (IPC1-7): G11C11/417
Attorney, Agent or Firm:
Akira Koike (2 outside)