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Title:
FORMATION FOR LOW-RESISTANCE SINGLE CRYSTAL REGION
Document Type and Number:
Japanese Patent JPS60193379
Kind Code:
A
Abstract:

PURPOSE: To enable to obtain a clean forming method in such a way that the gate length on a mask and the actual gate length coincide with each other by a method wherein an anisotropic etching and a selective-and-epitaxial growth are combined together.

CONSTITUTION: An oxide film 2 is formed on the surface of a P type Si substrat 1, and after that, a polycrystalline Si film 3, which is used as a gate, is deposited thereon. After an Si nitriding film 4 was deposited on the polycrystalline Si film 3, the film 4 and the film 3 are performed a patterning. The Si nitriding film 4 is further deposited, the Si nitriding film only deposited on the film 2 is removed, and moreover, the film 2 is removed excluding the film 2 just under the Si film 3. As a result, the film 3 is covered with an Si nitriding film 4'. Regions, from where the silicon film 3 is exposing, are etched using an anisotropic etching solution and grooves 5 are formed. An Si film is made to selectively and epitaxially grow in the regions only of the grooves 5 while an impurity is doped and low resistant single crystal regions 6 are formed. As a result, a trouble of contamination, which easily occurs in the process, doesnot generate and the difference between the gate length on a mask and the actual gate length can be reduced.


Inventors:
KITAJIMA HIROSHI
Application Number:
JP4983584A
Publication Date:
October 01, 1985
Filing Date:
March 15, 1984
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/205; H01L29/78; (IPC1-7): H01L21/205
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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