Title:
DIAGNOSTIC SYSTEM FOR SEQUENCE CONTROLLER
Document Type and Number:
Japanese Patent JP3104761
Kind Code:
B2
Abstract:
PURPOSE: To obtain the controller diagnostic system having high reliability by executing a program as an input/output signal by inverting a bit of trace data, and comparing its result and the trace data.
CONSTITUTION: When a dual object is executed, an instruction at the time of executing an execution object and a dual instruction are executed in a CPU 1. On a data memory 3, data whose bit is inverted completely from the time of executing the execution object is inputted and outputted. In this case, unless there is abnormality in the CPU 1 and the data memory 3, a value obtained by executing a bit inversion of a result of execution coincides with trace data of an execution mode. On the contrary, in the case there is abnormality in the CPU 1 and an AND operation and an OR operation cannot be processed normally, and in the case there is abnormality in the data memory 3 and a certain bit is always turned on and off, the value obtained by executing a bit inversion of a result of execution does not coincide with the trace data of the execution mode. In such a way, a diagnosis of the CPU and the data memory can be executed with high reliability.
Inventors:
Nakamura Akio
Keisei Inoue
Keisei Inoue
Application Number:
JP25436191A
Publication Date:
October 30, 2000
Filing Date:
September 05, 1991
Export Citation:
Assignee:
Yaskawa Electric Co., Ltd.
International Classes:
G05B19/05; G05B19/048; G05B23/02; G06F11/14; G06F11/22; (IPC1-7): G05B19/048; G05B23/02; G06F11/14; G06F11/22
Domestic Patent References:
| JP619732A | ||||
| JP61183705A | ||||
| JP6218826A | ||||
| JP6073731A |