To provide a transformer that can improve a DC superposition characteristic without causing an eddy current loss.
An opposite region of a plate core 3 opposite to a top surface 23U is provided with a first opposite portion 31 that is not opposite to an input terminal 6 and an output terminal 7, and second opposite portions 32 that are opposite to the input terminal 6 and the output terminal 7. Between the top surface 23U and the first opposite portion 31, spacers 34, 34 form a first clearance d1. Between the input terminal 6 and the output terminal 7 and the second opposite portions 32, recesses of the plate core 3 corresponding to the second opposite portions 32 form a second clearance d2 larger than the first clearance d1. A magnetic flux passes between the top surface 23U and the first opposite portion 31, where the first clearance d1 is formed, and less of it passes between the input terminal 6 and the output terminal 7 and the plate core 3, where the second clearance d2 larger than the first clearance d1 is formed.
| WO/2009/148072 | CHIP INDUCTOR AND MANUFACTURING METHOD THEREOF |
| JP2023075711 | COIL DEVICE |
| JP2002075738 | COIL AND COIL PARTS USING THE SAME |
HARADA HIDEAKI
TSUCHIDA SETSU
KAWAHARA KEISUKE
| JP2004146671A | 2004-05-20 | |||
| JP2004146683A | 2004-05-20 | |||
| JP2005310947A | 2005-11-04 | |||
| JP2006073958A | 2006-03-16 | |||
| JP2006142205A | 2006-06-08 | |||
| JP2003234218A | 2003-08-22 | |||
| JP2004146671A | 2004-05-20 | |||
| JP2004146683A | 2004-05-20 | |||
| JP2005310947A | 2005-11-04 | |||
| JP2006073958A | 2006-03-16 | |||
| JP2006142205A | 2006-06-08 |
Yoshiki Kuroki
Takashi Mikami
Yasunori Ishizaka