To improve the availability of a buffer by using both buffers respectively exclusive for transmission and reception as buffers for transmission/reception at the time other than loop back operation.

At the time of normal transmission, MPU 1 transmits a transmission mode to a buffer manager 10 to start an output controller 5 with a transmission start signal TXE and to switch multiplexer 21 and 22 to the output side of MPU. Next, by synchronizing with a write signal WR, MPU makes an in- clock IN outputted from the manager to write data in the whole area of buffers 33H and 33L in this order. At this time the manager looks at a pointer PIU to switch to 33H to 33L. On the other hand, the controller 5 synchronizes with its own out-clock OUT to make the out-clock OUT outputted from the manager to 33H and 33L and reads data in the order of 33H and 33L to serial-convert it by a P-S conversion circuit 4 to be outputted to a transmission line. At this time, the manager looks at a pointer POU to switch a multiplexer 24 to 33H to 33L.