PURPOSE: To ensure a high speed operation and the high stability of a variable divider by inputting an input signals in common to the 1st-3rd clock input terminals and taking the output signal out of a 1st non-inverted electronic terminal or an inverted output terminal.

CONSTITUTION: The signal of the output terminal of a non-inverted Q2 of a data latch flip-flop DFF 2 is applied to the input terminal of a D11 of a DFF 1. The signal of the output terminal of a non-inverted Q3 of a DFF 3 is applied to the input terminal of a D12. The output is obtained from the output terminals of a non-inverted Q1 and an inverted Q1 of the DFF 1 respectively. Then the input clock signal Vin are applied to the input terminals of a non-inverted CP1, a non-inverted CP2, and a non-inverted CP3 of the DFF 1-3 respectively. Thus the frequency signal obtained by dividing the frequency of the signal Vin down to 1/4 with the mode control signal M kept at H and the signal obtained by dividing the frequency of the signal Vin down to 1/5 with the signal M kept at L are outputted to the output terminals 8 and 9 through the output terminals of the non-inverted Q1 and the inverted Q1 of the DFF 1 respectively and synchronously with the signal Vin.