To accelerate an operating speed of a PLL circuit using a 4-to-1 multiplexer and to reduce power consumption thereof.

The 4-to-1 multiplexer 1 for selecting one signal from among signals whose phases are 0°, 90°, 180° and 270° formed based upon a signal obtained by dividing a frequency of a signal from a voltage controlled oscillator (VCO) into predetermined stages, is composed of first to fourth AND gates 2-5 to which the signals of the respective phases and selection control signals C1-C4 for selecting the signals of the respective phases are respectively supplied, and a wired OR gate 6 for wired OR connection of the first-fourth AND gates 2-5. In the AND gates 2-5, signal processing is then performed in the form of a current signal, and the form of current is converted into the form of voltage by resistors 19-22 to obtain an output. Signal processing is performed in the form of current signal, thereby easily accelerating the operating speed and reducing power consumption.