PURPOSE: To set a frequency division ratio of a small circuit scale optionally by using a delay signal outputted from a binary element to frequency-divide an oscillation oscillating frequency.
CONSTITUTION: A pre-stage Q output terminal is connected to a D input terminal of a next stage, a clock pulse is inputted only to a 2nd stage D flip-flop 2 via an inverter 6, and inputted directly to each clock terminal of other D flip- flops 1,3-5. The output of the other D flip-flops 1,3-5 is inputted to a selector 7, the output terminal of the selector 7 is connected to the D terminal of a 1st stage flip-flop 1 via an inverter 8 to form a loop. The each Q output of 1st stage and 2nd stage D flip-flops 1, 2 is outputted via an exclusive OR circuit 9 to obtain a frequency division output. Since a 1st clock pulse after release of reset is outputted even when any frequency is selected, no spike is caused.
| JPS5826697 | [Title of the Invention] Ring counter |
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| JPS58142632 | SELF-RESTORING SYSTEM OF RING COUNTER |
ARISAWA YASUO
TASHIRO YOZO
KAWASAKI TETSUYA
