VERIFICATION METHOD AND VERIFICATION DEVICE OF CHARGE-UP DAMAGE

Japanese Patent JP2012146894

A

To provide a verification method or the like of charge-up damage, which uses an antenna rule applicable both to macro or the like and the whole semiconductor integrated circuit, by handling the wiring and the non-wiring separately.

The verification method of charge-up damage includes: a first step S10 for setting the upper limit of antenna ratio of each wiring layer based on the hierarchical number of an attention wiring layer and the total number of wiring layers; a second step S20 for calculating the area of a node imparting a charge-up damage to a given gate for each wiring layer based on layout data of a semiconductor integrated circuit, and determining the integrated value with the area of the same node included in a lower wiring layer; and a third step S30 for determining the antenna ratio of a node imparting a charge-up damage to a given gate included in an attention module, for each module of the semiconductor integrated circuit, based on the integrated value of the area up to the highest wiring layer of the attention module and the area of a given gate, and comparing the antenna ratio with the upper limit of antenna ratio in the highest wiring layer of the attention module.

WO/2001/037148	IP BASE LSI DESIGNING SYSTEM AND DESIGNING METHOD
JPS58147227	TRANSITION DETECTOR
JPH0590497	MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE MANUFACTURED THEREBY

CHIKAMOTO MOTONORI

JP2011005569A

August 02, 2012

January 14, 2011

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SEIKO EPSON CORP

H01L21/82; G06F17/50

Masahiko Ueyanagi
Osamu Suzawa
Kazuhiko Miyasaka

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