Title:
VERTICAL MOSFET
Document Type and Number:
Japanese Patent JPH01111378
Kind Code:
A
Abstract:
PURPOSE:To reduce a capacitance value between a gate and a drain by a method wherein a third semiconductor region which is of a first conductivity type and whose resistivity is lower than that of a second semiconductor layer is formed near the surface inside the second semiconductor layer. CONSTITUTION:An N-type semiconductor region 10 is formed near the surface of an N-type epitaxial layer 2 after one part of a gate electrode 4 in a region where the gate electrode 4 is superposed via a gate insulating film 3 on the surface of the N-type epitaxial layer 2 has been removed and while the removed gate electrode is used as a mask. Accordingly, a current path in an ON state is secured by the N-type semiconductor region 10 which has been formed on the surface of the N-type epitaxial layer 2; a width W2 to be removed of the gate electrode 4 can be made wider than a width to be removed of a conventional vertical-type MOSFET. By this setup, a capacitance value between a gate and a drain can be reduced sharply; a switching duration can be shortened and switching loss can be reduced.
Inventors:
SAKAI TATSURO
YAMASHITA NOBUHIKO
MURAKAMI NAOKI
YAMASHITA NOBUHIKO
MURAKAMI NAOKI
Application Number:
JP26984487A
Publication Date:
April 28, 1989
Filing Date:
October 26, 1987
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H01L29/78; H01L29/08; H01L29/423; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Masaki Yamakawa (1 person outside)