Title:
ELECTRONIC IRIS CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JP3134585
Kind Code:
B2
Abstract:
PURPOSE: To prevent picture quality from being deteriorated due to the adverse effect of an output change of a comparator circuit onto a video signal for a vertical effective period by operating the comparator circuit only for a vertical blanking period.
CONSTITUTION: Comparator circuits 10a, 10b are operated only when they receive an enable signal and a pulse is generated at a specific point of time within a vertical blanking period by a delay circuit 12 and a NAND circuit NAND to be impressed to the comparator circuits 10a, 10b as the enable signal. Moreover, the delay circuit 12 formed by connecting 4 flip-flop circuits F/F in cascade receives a horizontal synchronizing signal as a clock pulse to delay a vertical blanking signal VBLK and the NAND circuit NAND receives an output signal of the delay circuit 12 an inverted output signal of the flip-flop F/F at a stage before the final stage to generate the enable signal having a pulse width equivalent to one horizontal period. Thus, the output signal from the comparator circuits 10a, 10b is not changed during the vertical effective period.
Inventors:
Masanori Yamaguchi
Application Number:
JP7754693A
Publication Date:
February 13, 2001
Filing Date:
March 11, 1993
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N5/335; H04N5/353; H04N5/357; H04N5/369; H04N5/372; H04N5/378; (IPC1-7): H04N5/335
Domestic Patent References:
| JP548975A | ||||
| JP432380A |
Attorney, Agent or Firm:
Hideaki Ogawa