Title:
VOLTAGE GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP3134798
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a voltage generating circuit for multileveled cell capable of outputting outputs linked with fluctuations of threshold voltage due to positions of selected memory cell transistors.
SOLUTION: This voltage generating circuit is provided with partial circuits 101∼105 of the same number of stages at that of memory cell transistors and the respective partial circuits 101∼105 are respective provided with cell partial circuits 106∼110 and respective cell partial circuits 106∼110 have memory transistors and resistances and respective resistances are set to be resistance values equal to resistance values to be parastically added to source terminals and drain terminals of memory cell transistors. Then, voltages linked with fluctuations of threshold voltage to be generated by differences between source potentials and substrate potentials are generated by connecting the same signals as that of word lines to the partial circuits 101∼105 and by selecting the partial circuit equal to a memory cell transistor whose word line is selected.
Inventors:
Takayuki Suzu
Kenji Hibino
Kenji Hibino
Application Number:
JP32082796A
Publication Date:
February 13, 2001
Filing Date:
November 15, 1996
Export Citation:
Assignee:
NEC
International Classes:
G11C5/14; G11C16/02; G11C16/06; G11C17/12; (IPC1-7): G11C16/02; G11C16/06
Domestic Patent References:
| JP5234389A | ||||
| JP62204496A |
Attorney, Agent or Firm:
Asamichi Kato