Title:
VOLTAGE LEVEL CONTROLLER FOR LOGICAL SIGNAL AND INTERFACE METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3121252
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a voltage level controller for a logical signal which doesn't occupy a physically large space and can easily be produced collectively.
SOLUTION: The voltage level of an external bus is sampled, and a voltage detection circuit 12 performs the control based on the storage result to control both an output driver 16 and an input receiver 18. A logical signal level for input/output(I/O) interface generated as the result is maintained within an allowable range of a standard I/O signal level.
Inventors:
Philip W. Bringer
Michael Jay McManus
Michael Jay McManus
Application Number:
JP32009695A
Publication Date:
December 25, 2000
Filing Date:
December 08, 1995
Export Citation:
Assignee:
Symbios Incorporated
International Classes:
G06F3/00; H03K19/0175; H03K19/0185; (IPC1-7): H03K19/0175; G06F3/00
Domestic Patent References:
| JP435220A | ||||
| JP353712A |
Other References:
【文献】米国特許5084637(US,A)
Attorney, Agent or Firm:
Yoshiaki Nishiyama