Title:
WAFER PROCESSING METHOD
Document Type and Number:
Japanese Patent JP2022064088
Kind Code:
A
Abstract:
To provide a novel technique for reducing occurrence of chips and cracks on a rear face of a chip, in a processing method that includes attaching a warped wafer to a tape and then performing processing to divide the wafer.SOLUTION: Warpage of a wafer W is eliminated in a pre-stage of subsequent cutting and internal stress of the wafer W is relieved, so that, by an action of the internal stress in the cutting, occurrence of chips and cracks due to concentration of stress around a cutting groove can be suppressed.SELECTED DRAWING: Figure 4
Inventors:
CHEN JUNG SHIANG
Application Number:
JP2020172604A
Publication Date:
April 25, 2022
Filing Date:
October 13, 2020
Export Citation:
Assignee:
DISCO ABRASIVE SYSTEMS LTD
International Classes:
H01L21/301; B23K26/364; B24B1/00; B24B27/06
Attorney, Agent or Firm:
Hiroshi Ogami
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