配線基板及びその製造方法

Title:

配線基板及びその製造方法

Document Type and Number:

Japanese Patent JP7424520

Kind Code:

B2

Abstract:

A wiring substrate capable of providing a through electrode having an insulating layer with a small dielectric loss is provided. A wiring substrate (50) includes a silicon substrate (40) formed of silicon whose electrical resistivity is 1000 Ω·cm or larger and a through electrode (100) formed in the silicon substrate (40). The through electrode (100) is formed of a central conductor (110) that penetrates through the silicon substrate (40) and an external conductor (120, 130, 140) formed around the central conductor (110). The central conductor (110) and the external conductor (120, 130, 140) are electrically insulated from each other by the silicon substrate (40).

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Inventors:

Hide Watanabe
West Virtue

Application Number:

JP2023000961A

Publication Date:

January 30, 2024

Filing Date:

January 06, 2023

Export Citation:

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Assignee:

NEC

International Classes:

H01L23/12; H01L21/3205; H01L21/768; H01L23/14; H01L23/522; H05K1/02; H10N60/80

Domestic Patent References:

JP2002334956A
JP2004356160A
JP2016066770A
JP2006019455A

Foreign References:

US20190273197
US20100295066
CN109461699A
CN103311141A
CN106158835A

Attorney, Agent or Firm:

Ken Ieiri

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