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Patent Searching and Data


Title:
WIRING METHOD FOR EQUAL-LENGTH SPECIFIED NETWORK
Document Type and Number:
Japanese Patent JPH06124322
Kind Code:
A
Abstract:

PURPOSE: To reduce influence on a via hole which is already designed and other wiring patterns, and to suppress radiation noises and reduce the distortion of a signal waveform when the equal-length specified network which is already designed and wired is equalized in length as to the wiring method for the equal- length specified network of a wiring pattern which is wired on a printed circuit board.

CONSTITUTION: This wiring method for the equal-length specified network nearly equalizes signal delay times between plural equal-length series which are already designed in terms of the length of wiring, etc.; and equal-length series which are shorter in wiring length than the longest equal-length series among plural equal-length series which are already designed are divided into orthogonal X-directional and Y-directional layers, and wirings (a) and (b) which are arranged between the start points and end points of the equal length series by the X-directional layer and Y-directional layer are folded and extended for by-passing once from at least one point to outside the prolongations connecting the start points and end points, so that the electric conductors become nearly equal in wiring length.


Inventors:
YAMAGUCHI TAKAO
Application Number:
JP27210192A
Publication Date:
May 06, 1994
Filing Date:
October 12, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H05K3/00; G06F17/50; (IPC1-7): G06F15/60; H05K3/00
Attorney, Agent or Firm:
Teiichi