Title:
WORD LINE DRIVING CIRCUIT
Document Type and Number:
Japanese Patent JPH08339689
Kind Code:
A
Abstract:
To obtain a word line driving circuit which can be operated to receive address signals from a decoder circuit and to output the received address signals to one or a plurality of memory cells in a RAM as word line signals by gating.
A word line driving circuit is constituted so that none of its internal nodes 112, 113, 114, and 115 provided between circuit elements can have any floating potential. Therefore, the oscillation of outputted word line signals can be prevented. This function is fulfilled by means of a plurality of circuit elements individually arranged to prevent the floating of internal nodes.
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Inventors:
MANOJI KUMARU
JIYOOZEFU EMU POPURAFUSUKI JIY
JIYOOZEFU EMU POPURAFUSUKI JIY
Application Number:
JP12807196A
Publication Date:
December 24, 1996
Filing Date:
May 23, 1996
Export Citation:
Assignee:
IBM
International Classes:
G11C11/413; G11C8/08; G11C11/407; (IPC1-7): G11C11/413; G11C11/407
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)
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