To suppress the power consumption of a multi-bank type semiconductor memory device by providing a transistor which receives a bank selecting signal at its gate and another transistor which receives the inverted signal of the bank selecting signal at its gate.
The memory array of a multi-bank type semiconductor memory device is divided into (n) pieces of banks B0-Bn. No individual column decoder is provided for each bank, but one common column decoder 20 is provided to the banks. K pieces of global column selecting lines GCSLO-GCSLK (K: a natural number) led out from the decoder 20 and extended in the direction of bit lines are provided in common to all banks. Therefore, the occurrence of such a case that dummy data are transmitted to a nonselected sub-input- output line can be prevented by means of a switch using bank selecting signals.
JPH03154287A | 1991-07-02 | |||
JPH0574165A | 1993-03-26 | |||
JPH03181094A | 1991-08-07 |