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Title:
MULTI-BANK TYPE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH08339687
Kind Code:
A
Abstract:

To suppress the power consumption of a multi-bank type semiconductor memory device by providing a transistor which receives a bank selecting signal at its gate and another transistor which receives the inverted signal of the bank selecting signal at its gate.

The memory array of a multi-bank type semiconductor memory device is divided into (n) pieces of banks B0-Bn. No individual column decoder is provided for each bank, but one common column decoder 20 is provided to the banks. K pieces of global column selecting lines GCSLO-GCSLK (K: a natural number) led out from the decoder 20 and extended in the direction of bit lines are provided in common to all banks. Therefore, the occurrence of such a case that dummy data are transmitted to a nonselected sub-input- output line can be prevented by means of a switch using bank selecting signals.


Inventors:
YANAGI SEIKAN
Application Number:
JP11756596A
Publication Date:
December 24, 1996
Filing Date:
May 13, 1996
Export Citation:
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Assignee:
SAMSUNG ELECTRONIC
International Classes:
G11C8/12; G11C11/41; G11C11/40; G11C11/401; G11C11/409; (IPC1-7): G11C11/41
Domestic Patent References:
JPH03154287A1991-07-02
JPH0574165A1993-03-26
JPH03181094A1991-08-07
Attorney, Agent or Firm:
Takeshi Takatsuki



 
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