Title:
XOR GATE
Document Type and Number:
Japanese Patent JP2008071922
Kind Code:
A
Abstract:
To provide an XOR gate suitable for the high integration of LSI.
A first Fin 111 and a second Fin 112 are formed on a semiconductor substrate 100. An nFET1 and a pFET3 are formed in the one side of the first Fin 111 and a pFET1 and a pFET4 are formed in another side so as to oppose the each MISFET. Moreover, an nFET2 and an nFET3 are formed in the one side of the second Fin 112 and a pFET2 and an nFET4 are formed in another side so as to oppose the each MISFET. An XOR gate with a substantial part constituted by MISFET having a three dimensional structure as described above is provided.
Inventors:
MATSUZAWA KAZUYA
Application Number:
JP2006249024A
Publication Date:
March 27, 2008
Filing Date:
September 14, 2006
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L21/8238; H01L27/08; H01L27/092; H01L29/786
Attorney, Agent or Firm:
Mitsuyuki Matsuyama
Tetsuma Ikegami
Tetsuma Ikegami