表示装置、電子機器 - Semiconductor Energy Laboratory Co., Ltd.

Title:

表示装置、電子機器

Document Type and Number:

Japanese Patent JP7183370

Kind Code:

B2

Abstract:

To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

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Inventors:

Junichiro Sakata
Hiromitsu Godo
Takashi Shimazu

Application Number:

JP2021179946A

Publication Date:

December 05, 2022

Filing Date:

November 04, 2021

Export Citation:

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Assignee:

Semiconductor Energy Laboratory Co., Ltd.

International Classes:

H01L29/786; G02F1/1368; G09F9/30; H01L21/336; H01L51/50; H05B33/14

Domestic Patent References:

JP200796055A
JP2008205469A
JP200773559A

Foreign References:

US20080299702

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