Title:
電子制御装置
Document Type and Number:
Japanese Patent JP7342669
Kind Code:
B2
Abstract:
To suppress the increase in CPU core processing load due to interrupt processing.SOLUTION: An ECU 1 includes CPU cores 11 to 14, a request control register, and an interrupt controller 17. The request control register stores, for each of a plurality of interrupt factors, core designation information that designates CPU cores 11 to 14 that generate interrupts due to the interrupt factors. When the interrupt factors occur, the interrupt controller 17 generates interrupts for the corresponding CPU cores 11 to 14 based on the core designation information. Each of the CPU cores 11 to 14 determines about a processing execution core whether it is necessary to cause the CPU cores 11 to 14 to vicariously execute interrupt processing, as the processing execution core. When it is determined that a vicarious execution is necessary, the CPU cores 11 to 14 select one vicarious execution object core. The CPU cores 11 to 14 change the core designation information so that the selected vicarious execution core executes the interrupt processing.SELECTED DRAWING: Figure 1
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Inventors:
Kazuyuki Okuda
Hiroo Kokubu
Hiroo Kokubu
Application Number:
JP2019219680A
Publication Date:
September 12, 2023
Filing Date:
December 04, 2019
Export Citation:
Assignee:
株式会社デンソー
International Classes:
G06F9/48
Domestic Patent References:
| JP2008269549A | ||||
| JP2019109744A | ||||
| JP2010134689A | ||||
| JP9237255A |
Foreign References:
| WO2010010723A1 |
Attorney, Agent or Firm:
Nagoya International Patent Attorney Corporation