Title:
A manufacturing method of an imaging device
Document Type and Number:
Japanese Patent JP6184493
Kind Code:
B2
Abstract:
A gate electrode of a field effect transistor is formed. Next, an offset spacer film with a double-layer structure including a silicon oxide film as a lower-layer film and a silicon nitride film as an upper-layer film is formed on a sidewall surface of the gate electrode. The silicon nitride film serves as a supply source of an element for terminating dangling bonds of silicon in a device formation region. Next, treatment for leaving the offset spacer film intact or treatment for removing the silicon nitride film of the offset spacer film is performed. Thereafter, a sidewall insulating film is formed on the sidewall surface of the gate electrode.
Inventors:
Takahiro Tomimatsu
Application Number:
JP2015522366A
Publication Date:
August 23, 2017
Filing Date:
June 14, 2013
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L27/146; H01L21/822; H01L21/8238; H01L27/04; H01L27/088; H01L27/092
Domestic Patent References:
| JP2006216615A | ||||
| JP2009026848A | ||||
| JP2010212536A | ||||
| JP2011155248A | ||||
| JP2007294540A | ||||
| JP2010283859A | ||||
| JP2003092403A | ||||
| JP2004103571A |
Foreign References:
| US20120175707 | ||||
| WO2010122657A1 |
Attorney, Agent or Firm:
Fukami patent office