Title:
ウエハーの接合中に欠陥を処理するプロセス
Document Type and Number:
Japanese Patent JP2011510495
Kind Code:
A
Abstract:
The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
Inventors:
Christel Ragae
Bernard Aspal
Bernard Aspal
Application Number:
JP2010542633A
Publication Date:
March 31, 2011
Filing Date:
January 16, 2009
Export Citation:
Assignee:
S.O.I.Tech Silicon on Insulator Technologies
International Classes:
H01L21/02; H01L27/12
Domestic Patent References:
| JPH11297972A | 1999-10-29 | |||
| JPH07161596A | 1995-06-23 | |||
| JP2006517734A | 2006-07-27 | |||
| JP2007227415A | 2007-09-06 |
Other References:
JPN3001004420; 斉藤雄一: 'ＳＯＩ基板材料' ＵＬＳＩプロセス材料実務便覧 第１版, 19920130, Ｐ６３-７０, サイエンスフォーラム
Attorney, Agent or Firm:
Yoshikazu Tani
Kazuo Abe
Kazuo Abe