Title:
a semiconductor integrated circuit device
Document Type and Number:
Japanese Patent JP5917858
Kind Code:
B2
Abstract:
An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
Inventors:
Natsuki Ikebata
Kazuo Tanaka
Takeo Toba
Arakawa Masashi
Kazuo Tanaka
Takeo Toba
Arakawa Masashi
Application Number:
JP2011185608A
Publication Date:
May 18, 2016
Filing Date:
August 29, 2011
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03F3/45; H03K19/0175
Domestic Patent References:
| JP2001320243A | ||||
| JP2009049672A | ||||
| JP2009094640A |
Foreign References:
| US20080054949 |
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji