Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP7273668
Kind Code:
B2
Abstract:
According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.
Inventors:
Koichi Shinohara
Katsuki Matsudera
Gamarra Ian Christopher
Yoshikazu Harada
Noritaka Kai
Yusuke Tanefusa
Katsuki Matsudera
Gamarra Ian Christopher
Yoshikazu Harada
Noritaka Kai
Yusuke Tanefusa
Application Number:
JP2019166809A
Publication Date:
May 15, 2023
Filing Date:
September 13, 2019
Export Citation:
Assignee:
Kioxia Co., Ltd.
International Classes:
G11C16/34; G11C16/04; G11C16/16; G11C29/04
Domestic Patent References:
| JP2009252278A | ||||
| JP200654036A | ||||
| JP2011522351A | ||||
| JP2008159134A | ||||
| JP201325826A |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Shunichi Takahashi
Masakazu Ito
Toshio Takamatsu
Shunichi Takahashi
Masakazu Ito
Toshio Takamatsu