Title:
WIRING CIRCUIT, CONTROL DEVICE AND IMAGE PROCESSOR
Document Type and Number:
Japanese Patent JP2017027638
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To suppress the power consumption of DDR 3 memory modules, and to properly suppress the reflection of a data signal.SOLUTION: In a wiring circuit 11, a DIMM socket 3 is connected to a branch point DP1 which is arranged on a signal line L1, and when a clock frequency is lower than a reference frequency, a control circuit 4 inactivates an ODT function of an access module 2 (31) being an output destination of the data signal out of first and second DDR 3 memory modules 2, 31, activates an ODT function of a non-access module 31 (2) which is not the output destination of the data signal, and sets the ODT function to use the prescribed terminal end resistance of a first resistance value, and when the clock frequency is not lower than the reference frequency, the control circuit activates the ODT function of the access module 2 (31), and sets the ODT function to use the terminal end resistance of the first resistance value, activates the ODT function of the non-access module 31 (2), and sets the ODT function to use the terminal end resistance of a second resistance value which is smaller than the first resistance value.SELECTED DRAWING: Figure 2
Inventors:
LIU CHE
Application Number:
JP2015141941A
Publication Date:
February 02, 2017
Filing Date:
July 16, 2015
Export Citation:
Assignee:
KYOCERA DOCUMENT SOLUTIONS INC
International Classes:
G11C5/00; G06F12/00
Attorney, Agent or Firm:
Etsushi Kotani
Masataka Otani
Koji Nishitani
Masataka Otani
Koji Nishitani