Title:
AMPLIFICATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/235140
Kind Code:
A1
Abstract:
This amplification circuit is provided with: an amplifier (5) that includes an amplification transistor (10); and a bias circuit (1). The bias circuit (1) includes: a bias transistor (22) that has a base terminal (B1) and a collector terminal (C1); a transistor (33) that has a gate terminal (G2), a source terminal (S3), and a drain terminal (D4); a transistor (31) that has a gate terminal (G3), a source terminal (S5), and a drain terminal (D6); resistors (41 and 42); and a current source (60). The source terminals (S3 and S5) are connected to a power supply. One end of the resistor (42) is connected to the base terminal (B1). Another end of the resistor (42) is connected to the drain terminal (D6). One end of the resistor (41) is connected to another end of the resistor (42). Another end of the resistor (41) is connected to a bias output terminal (100). The amplification circuit is further provided with a feedback circuit that controls electric potential of the base terminal (B1) on the basis of electric potential of the collector terminal (C1).
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Inventors:
NASU KOUJI (JP)
Application Number:
PCT/JP2021/015232
Publication Date:
November 25, 2021
Filing Date:
April 12, 2021
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03F1/30; H03F3/21; H03F3/343
Foreign References:
| JP2002232238A | 2002-08-16 | |||
| JP2005228196A | 2005-08-25 | |||
| US20070139120A1 | 2007-06-21 | |||
| US20160190992A1 | 2016-06-30 | |||
| JP2015046876A | 2015-03-12 | |||
| US20180152155A1 | 2018-05-31 |
Attorney, Agent or Firm:
YOSHIKAWA, Shuichi et al. (JP)
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