Title:
ANTI-FUSE CIRCUIT, STRUCTURE, ARRAY, PROGRAMMING METHOD AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/065909
Kind Code:
A1
Abstract:
The present disclosure relates to the field of semiconductors, and in particular, to an anti-fuse circuit, structure, array, programming method and memory. The anti-fuse circuit comprises: an anti-fuse, a select transistor and a clamping capacitor. A first end of the anti-fuse is configured to receive a programming signal. A gate of the select transistor is configured to receive a selection signal, and a first electrode of the select transistor is configured to receive a bit line voltage. A first end of the clamping capacitor is configured to receive a preset voltage. A second end of the anti-fuse, a second electrode of the select transistor and a second end of the clamping capacitor are coupled to each other. By adding the clamping capacitor between the anti-fuse and the select transistor, due to the potential clamping effect of the clamping capacitor, when the anti-fuse is programmed, a sharp rise in potential at the second end of the anti-fuse is avoided, that is, the voltage difference between the two ends of the anti-fuse is maintained, thereby ensuring successful writing to the anti-fuse when the width of a select transistor device is reduced.
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Inventors:
HOU CHUANGMING (CN)
Application Number:
PCT/CN2022/127090
Publication Date:
April 04, 2024
Filing Date:
October 24, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C17/16
Foreign References:
| CN105513643A | 2016-04-20 | |||
| CN1801620A | 2006-07-12 | |||
| CN109524402A | 2019-03-26 | |||
| CN112234061A | 2021-01-15 |
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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