APPARATUS AND CIRCUIT FOR PROCESSING CARRIER AGGREGATION

Title:

APPARATUS AND CIRCUIT FOR PROCESSING CARRIER AGGREGATION

Document Type and Number:

WIPO Patent Application WO/2014/148730

Kind Code:

A1

Abstract:

A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.

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Inventors:

DO JOO-HYUN (KR)
KIM IN-HYOUNG (KR)

Application Number:

PCT/KR2014/000090

Publication Date:

September 25, 2014

Filing Date:

January 06, 2014

Export Citation:

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Assignee:

SAMSUNG ELECTRONICS CO LTD (KR)

International Classes:

H04L27/26; H04L7/00

Foreign References:

US7848397B2	2010-12-07
US20120213190A1	2012-08-23
US20120213096A1	2012-08-23
US7680236B1	2010-03-16
US20100296389A1	2010-11-25

Other References: