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Title:
APPARATUS AND METHOD FOR DECODING A PLURALITY OF CODEWORDS
Document Type and Number:
WIPO Patent Application WO/2023/102794
Kind Code:
A1
Abstract:
An apparatus for decoding a plurality of codewords. The apparatus comprises one or more decoding blocks associated with a clock having a clock cycle, such that each of the decoding blocks are configured to receive in input a plurality of codewords. A given decoding block comprises a plurality of decoding units arranged in series, each of the decoding unit in the plurality of decoding units being configured to run a decoding stage. The plurality of decoding units comprise M identical series of N decoding units, with M >1 and N >1 forming a series of N x M decoding units. The given decoding block is configured to receive in input each codeword, amongst the plurality of codewords, one after the other every C clock cycles, with 0 < C < N x M.

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Inventors:
BEN-ARIE YARON (DE)
EPSTEIN AVNER (DE)
BASSON NADAV (DE)
SHILO SHIMON (DE)
LI WEN (CN)
EZRI DORON (DE)
Application Number:
PCT/CN2021/136602
Publication Date:
June 15, 2023
Filing Date:
December 08, 2021
Export Citation:
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Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03M13/11
Domestic Patent References:
WO2020108586A12020-06-04
WO2011144170A12011-11-24
Foreign References:
US20130154857A12013-06-20
JP2016082345A2016-05-16
US20060218458A12006-09-28
Other References:
CHANG CHAOPING; LIU SHAOHUA; WANG HAOLIN: "A low complexity FPGA implementation of uplink SCMA decoder", 2019 3RD INTERNATIONAL CONFERENCE ON ELECTRONIC INFORMATION TECHNOLOGY AND COMPUTER ENGINEERING (EITCE), IEEE, 18 October 2019 (2019-10-18), pages 1525 - 1529, XP033772072, DOI: 10.1109/EITCE47263.2019.9094807
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