BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modern terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various mechanisms for calibrating a radio frequency (RF) chip.

SUMMARY

[0003] Embodiments of apparatus and method of wireless communication are disclosed herein.

[0004] According to one aspect of the present disclosure, an RF chip is provided. The RF chip may include a plurality of sample paths configured to generate a plurality of sample streams. The RF chip may include a plurality of memory buffers coupled to the plurality of sample paths and configured to receive the plurality of sample streams. The RF chip may include a vector digital signal processor (vDSP). The vDSP may be configured to read the plurality of sample streams from the plurality of memory buffers concurrently. The vDSP may be configured to perform parallel processing of the plurality of sample streams to calibrate the plurality of sample paths.

[0005] According to another aspect of the present disclosure, a vDSP of an RF chip is provided. The vDSP may include a plurality of memory interfaces configured to interface with a plurality of memory buffers associated with a plurality of sample paths. The vDSP may include a plurality of processing engines coupled to the plurality of memory interfaces. The plurality of processing engines may be configured to read, via the plurality of memory interfaces, a plurality of sample streams from the plurality of memory buffers concurrently, the plurality of sample streams being associated with the plurality of sample paths. The plurality of processing engines may be configured to perform parallel processing of the plurality of sample streams to calibrate the plurality of sample paths.

[0006] According to yet another aspect of the present disclosure, a method of wireless communication of an RF chip is provided. The method may include generating, by a plurality of sample paths, a plurality of sample streams. The method may include receiving, by a plurality of memory buffers, the plurality of sample streams concurrently. The method may include reading, by a vDSP, the plurality of sample streams from the plurality of memory buffers concurrently. The method may include performing, by the vDSP, parallel processing of the plurality of sample streams to calibrate the plurality of sample paths.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0009] FIG. 2 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0010] FIG. 3 illustrates a detailed block diagram of the RF chip of FIG. 2, according to some embodiments of the present disclosure.

[0011] FIG. 4 illustrates a flow chart of an exemplary method of wireless communication, according to some embodiments of the present disclosure.

[0012] FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0013] FIG. 6 illustrates a conventional RF chip and baseband chip.

[0014] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0015] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0016] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0017] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0018] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system.

[0019] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0020] RF self-calibration refers to using the baseband chip and/or RF chip to measure and compensate for imperfections in the RF analog circuits rather than using external electronic lab equipment. There are various types of RF self-calibration procedures that may be performed to compensate for imperfections and optimize RF performance. These calibration procedures may include, e.g., receiver (Rx) gain calibration, in-phase/in-quadrature (IQ) mismatch calibration, power amplifier (PA) non-linearity calibration, a transmit (Tx) input-referred second-order intercept point (IIP2) calibration procedure, a Tx power calibration procedure, or antenna tuning.

[0021] RF self-calibration may be performed using waveform generators and processors located on the baseband chip and/or RF chip. For example, a waveform may be input through a sample path of the RF chip (e.g., the device-under-test (DUT)) so that a sample stream may be output. The sample stream, once obtained by processing units, may be processed in order to identify imperfections and calibrate the RF chip. An example apparatus that may perform RF selfcalibration is depicted in FIG. 6.

[0022] FIG. 6 illustrates a conventional apparatus 600 that performs RF self-calibration. Conventional apparatus 600 (referred to hereinafter as “apparatus 600”) includes a baseband chip 602 and an RF chip 604 that may be coupled by a serializer/deserializer (SerDes) 612. A plurality of Rx and Tx antennas 610 may be coupled to RF chip 604.

[0023] As shown in FIG. 6, RF chip 604 may include a plurality of sample paths 606, as well as a plurality of memory buffers 608 coupled thereto. In the example illustrated in FIG. 6, the plurality of sample paths 606 may include a first Rx sample path (Rxl), a second Rx sample path (Rx2), a Tx sample path (Txl), and a Tx auxiliary Rx (TAR) sample path (TAR1). Each of the sample paths 606 may be used to generate sample streams that processing unit 620 uses to perform different calibration procedures. [0024] Traditionally, RF self-calibration is performed serially. In other words, a first set of samples (also referred to herein as a “sample stream”) is captured by a first sample path (e.g., Rxl), followed by the processing of the first set of samples (by processing unit 620) to calibrate the first sample path; then, a second set of samples is captured by a second sample path (e.g., Rx2), followed by the processing of the second set of samples (by processing unit 620) to calibrate the second sample path, and so on. In conventional RF self-calibration, the limiting factor is either the serial sample capture or processing power consumed by processing unit 620. Additionally, because processing unit 620 is located on baseband chip 602, transferring the samples to baseband chip 602 causes additional delay and consumes an undesirable amount of power, due to signaling overhead between the RF chip 604 and baseband chip 602. Still further, conventional RF self-calibration uses a complex software-based processing unit 620, which further increases power consumption.

[0025] Thus, there exists an unmet need for a technique that provides RF self-calibration with reduced latency, lower power consumption, and less signaling overhead, as compared with known techniques.

[0026] To overcome these and other RF self-calibration challenges, the present disclosure provides a parallel sample stream processing technique (also referred to herein as “parallel RF selfcalibration technique”) that enables RF self-calibration with reduced latency, lower power consumption, and less signaling overhead, as compared with known techniques. For example, the parallel sample stream processing technique may be accomplished using a plurality of sample paths (e.g., Rx sample path, Tx sample path, and/or TAR sample path) configured to concurrently generate sample streams. Each sample path may have an associated memory buffer into which its sample stream is written. Rather than using a power hungry processing unit located on the baseband chip, the present disclosure provides a vDSP located on the RF chip. The vDSP may be coupled in parallel to the plurality of memory buffers via a plurality of memory interfaces. The vDSP may include a plurality of processing engines configured for parallel processing of the plurality of sample streams. In other words, each sample path may be associated with a dedicated set of processing engines of the vDSP, which enables parallel processing of all sample streams such that the sample paths are calibrated concurrently. Moreover, the memory buffers of the present disclosure may be configured for concurrent read and write operations such that while sample stream data is being written to the memory buffer, the vDSP may be simultaneously reading sample stream data from the memory buffer. By configuring an RF chip with parallel sample streams, memory buffers, and a vDSP with parallel processing engines, RF self-calibration may be achieved with reduced latency, lower power consumption, and with less signaling overhead, as compared with known approaches. Additional details of parallel RF self-calibration technique are provided below in connection with FIGs. 1-5.

[0027] FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0028] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation. [0029] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0030] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides quality-of-service (QoS) flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0031] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node. [0032] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0033] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG. 5. Node 500 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 500 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 106. Other implementations are also possible.

[0034] Transceiver 506 may include any suitable device for sending and/or receiving data. Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0035] As shown in FIG. 5, node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included. Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 502 may be a hardware device having one or more processing cores. Processor 502 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0036] As shown in FIG. 5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage. For example, memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502. Broadly, memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0037] Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions. In some embodiments, processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 502 and transceiver 506 (and memory 504 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0038] Referring back to FIG. 1, in some embodiments, user equipment 102 may perform a parallel sample stream processing technique that enables RF self-calibration with reduced latency, lower power consumption, and less signaling overhead, as compared with known techniques. The parallel sample stream processing technique may be accomplished by enabling a plurality of sample paths (e.g., Rx sample path, Tx sample path, and/or TAR sample path) of user equipment 102 to concurrently generate sample streams, which may be used for parallel RF self-calibration. Each sample path may have an associated memory buffer into which its sample stream may be written. Rather than using a power hungry processing unit located on the baseband chip, user equipment 102 includes a vDSP located on its RF chip. The vDSP may be coupled in parallel to the plurality of memory buffers via a plurality of memory interfaces. The vDSP may include a plurality of processing engines configured for parallel processing of the plurality of sample streams. In other words, each sample path may be associated with a dedicated set of processing engines of the vDSP. This enables parallel processing of all sample streams such that the sample paths are calibrated concurrently. Moreover, the memory buffers located on the RF chip of user equipment 102 may be configured for concurrent read and write operations. This means that while sample stream data is being written to the memory buffer by a sample path, the vDSP may be reading sample stream data from the memory buffer, simultaneously. By configuring the RF chip of user equipment 102 with parallel sample streams, memory buffers, and a vDSP with parallel processing engines, RF self-calibration may be achieved with reduced latency, lower power consumption, and with less signaling overhead, as compared with known approaches. Additional details of the parallel RF self-calibration technique are provided below in connection with FIGs. 2-4. [0039] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip 202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be implemented as user equipment 102 of wireless network 100 in FIG. 1. As shown in FIG. 2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG. 5. Besides the on-chip memory 218 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG. 2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.

[0040] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Interface 214 of baseband chip 202 may receive the data from host chip 206. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204 via interface 214. RF chip 204, through the transmitter (Tx) (e.g., Tx sample path(s)), may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 204.

[0041] In the downlink, antenna 210 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) (e.g., Rx sample path(s) 230b) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202.

[0042] Still referring to FIG. 2, apparatus 200 may perform a parallel sample stream processing technique that enables RF self-calibration of RF chip 204 with reduced latency, lower power consumption, and less signaling overhead, as compared with known techniques. The parallel sample stream processing technique may be accomplished by enabling a plurality of sample paths 230 (e.g., Tx sample path(s), Rx sample path(s), and/or TAR sample path(s)) of RF chip 204 to concurrently generate sample streams, which may be used for parallel RF selfcalibration. Each sample path may have an associated memory buffer 240 into which its sample stream may be written. Rather than using a power hungry processing unit located on baseband chip 202, apparatus 200 includes a vDSP 220 located on RF chip 204. The vDSP 220 may be coupled to the plurality of memory buffers 240 in parallel via a plurality of memory interfaces (see FIG. 3). vDSP 220 may include a plurality of processing engines (see FIG. 3) configured for parallel processing of the plurality of sample streams. In other words, each sample path 230 may be associated with a dedicated set of processing engines of vDSP 220, which enables parallel processing of all sample streams such that the sample paths may be calibrated concurrently. Moreover, the memory buffers 240 located on RF chip 204 may be configured for concurrent read and write operations. This means that while sample stream data is being written to a memory buffer 240 by a sample path 230, vDSP 220 may be reading sample stream data from the memory buffer 240 simultaneously. By configuring RF chip 204 with parallel sample streams (from sample paths 230), memory buffers 240, and vDSP 220, RF self-calibration may be achieved with reduced latency, lower power consumption, and less signaling overhead, as compared with known approaches. Additional details of the parallel RF self-calibration technique of RF chip 204 are provided below in connection with FIGs. 3 and 4.

[0043] FIG. 3 illustrates a detailed block diagram 300 of the RF chip 204 of FIG. 2, according to some embodiments. As shown in FIG. 3, RF chip 204 may include sample paths 230- 1 through 230-4 (collectively referred to as “sample paths 230”), memory buffers 240-1 through 240-4 (collectively referred to as “memory buffers 240”), and vDSP 220. Sample paths 230 may include any combination of Rx sample paths, Tx sample paths, and/or TAR sample paths.

[0044] In the example depicted in FIG. 3, the plurality of sample paths 230 includes a first Rx sample path (Rxl) 230-1, a second Rx sample path (Rx2) 230-2, a Tx sample path (Txl) 230- 3, and a TAR sample path (TAR1) 230-4. Each of Rxl sample path 230-1, Rx2 sample path 230- 2, and TAR1 sample path 230-4 may be configured to generate IQ sample streams, while Txl sample path 230-3 may be configured to generate a digital Tx sample stream. The number of sample paths 230 and types of sample streams generated are not limited to those depicted in FIG.

3. Rather, any number of Rx, Tx, and TAR sample paths may be included in RF chip 204 without departing from the scope of the present disclosure. The number of memory buffers 240 may be configured to match the number of sample paths 230, such that each sample path 230 has a dedicated memory buffer 240.

[0045] In the example illustrated in FIG. 3, there are four memory buffers 240: a first memory buffer (Meml) 240-1 associated with Rxl sample path 230-1, a second memory buffer (Mem2) 240-2 associated with Rx2 sample path 230-2, a third memory buffer (Mem3) 240-3 associated with Txl sample path 230-3, and a fourth memory buffer (Mem4) 240-4 associated with TAR1 sample path 230-4. Meml 240-1, Mem2 240-2, Mem3 240-3, and Mem4 240-4 may be configured to respectively receive the IQ sample stream of Rxl sample path 230-1, the IQ sample stream of Rx2 sample path 230-2, the digital Tx sample stream of Txl sample path 230-3, and the IQ sample stream of TAR1 sample path 230-4, concurrently.

[0046] As also shown in FIG. 3, vDSP 220 may include processing engines 350-1 through 350-4 (collectively referred to as “processing engines 350”) and a plurality of memory buffer interfaces 360. In some embodiments, the number of memory buffer interfaces 360 may be configured to match the number of memory buffers 240 and processing engines 350, and hence, the number of sample paths 230. By implementing parallel memory buffer interfaces 360 for each memory buffer 240, processing engines 350 of vDSP 220 may read sample streams from memory buffers 240, concurrently. For example, enginel 350-1 may read IQ sample stream data from Meml 240-1, engine2 350-2 may read IQ sample stream data from Mem2 240-2, engine3 350-3 may read digital Tx sample stream data from Mem3 240-3, and engine4 350-4 may read IQ sample stream data from Mem4 240-4, concurrently.

[0047] Each processing engine 350 may include a set of processing engines (e.g., one or more processing engines) dedicated to an associated sample path 230. Thus, by implementing parallel processing engines 350, vDSP 220 may perform parallel processing of the sample streams to calibrate various aspects of RF chip 204 (e.g., sample paths 230), concurrently. For example, enginel 3501 may calibrate the Rxl sample path 230-1, while engine2 350-2 concurrently calibrates the Rx2 sample path 230-2. In some embodiments, enginel 350-1 may calibrate the Rxl sample path 230-1, while engine3 350-3 concurrently calibrates the Txl sample path 230-3. In some embodiments, if the TAR1 sample path 230-4 is used to calibrate the Txl sample path 230- 3, TAR1 sample path 230-4 may stream Txl samples via coupler 310. In some embodiments, enginel 350-1, engine2 350-2, and engine3 350-3 may calibrate concurrently Rxl sample path 230-1, Rx2 sample path 230-2, and Txl sample path 230-3, respectively.

[0048] In some embodiments, each of the memory buffers 240 may be configured for concurrent read and write operations. This means that while sample stream data is being written to memory buffer 240 by a sample path 230, vDSP 220 may read sample stream data from the same memory buffer 240. Non-limiting examples of memory buffers 240 configured for concurrent read and write operations include dual-port memory buffers and/or ping-pong memory buffers.

[0049] As mentioned above, each of Rxl sample path 230-1, Rx2 sample path 230-2, and TAR1 sample path 230-4 may be configured to generate IQ sample streams, while Txl sample path 230-3 may be configured to generate a digital Tx sample stream. The sample streams generated by each of the sample paths 230 may be used by vDSP 220 for different calibration procedures. Non-limiting examples of the different calibration procedures that may be carried out in parallel by processing engines 350 may include any combination of an Rx gain calibration procedure, an IQ mismatch calibration procedure, a PA non-linearity cancellation calibration procedure, a Tx IIP2 calibration procedure, a Tx power calibration procedure, and/or antenna tuning. Non -limiting example operations for Rx gain calibration and IQ mismatch calibration are provided below. It is understood that, although not described in detail, other calibration techniques may be performed using different operations.

[0050] For example, for Rx gain calibration, a tone may be injected with known power at an input of an Rxl sample path 230-1. The Rxl sample path 230-1 may output an IQ sample stream to Meml 240-1. Enginel 350-1 may read the IQ stream from Meml 240-1 via its memory buffer interface 360. Then, enginel 350-1 may calculate I ² +Q ^2, which may be used for Rx gain calibration. In some embodiments, the Rx gain calibration procedure may be performed by enginel for Rxl sample path 230-1 and engine2 for Rx2 sample path 230-2, simultaneously.

[0051] For IQ mismatch calibration, one or more tones with different frequency offsets may be injected into Rxl sample path 230-1 to generate an IQ sample stream, which is written to Meml 240-1. Then, enginel 350-1 may read the IQ stream via memory buffer interface 360. Here, enginel 350-1 may correlate I with Q over time, calculate the mean of I, calculate the mean of Q, and/or calculate the I ² and Q ² . Then, these computations may be used to perform IQ mismatch calibration.

[0052] In this way, by configuring RF chip 204 for the generation of parallel sample streams, memory buffers 240, and processing engines 350, RF self-calibration may be achieved using the present techniques with reduced latency, lower power consumption, and with less signaling overhead, as compared with known approaches.

[0053] FIG. 4 illustrates a flowchart of an exemplary method 400 of wireless communication, according to embodiments of the disclosure. Exemplary method 400 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, RF chip 204, vDSP 220, sample paths 230, memory buffers 240, processing engines 350, memory buffer interfaces 360, and/or node 500. Method 400 may include steps 402-408 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4.

[0054] Referring to FIG. 4, at 402, the apparatus may generate a plurality of sample streams. For example, referring to FIG. 3, each of Rxl sample path 230-1, Rx2 sample path 230- 2, and TAR1 sample path 230-4 may be configured to generate IQ sample streams, while Txl sample path 230-3 may be configured to generate a digital Tx sample stream.

[0055] At 404, the apparatus may receive the plurality of sample streams at a plurality of memory buffers, concurrently. For example referring to FIG. 3, Meml 240-1, Mem2240-2, Mem3 240-3, and Mem4 240-4 may be configured to concurrently receive the IQ sample stream of Rxl sample path 230-1, the IQ sample stream of Rx2 sample path 230-2, the digital Tx sample stream of Txl sample path 230-3, and the IQ sample stream of TAR1 sample path 230-4, respectively.

[0056] At 406, the apparatus may read the plurality of sample streams from the plurality of memory buffers, concurrently. For example, referring to FIG. 3, vDSP 220 may include processing engines 350-1 through 350-4 (collectively referred to as “processing engines 350”) and a plurality of memory buffer interfaces 360. In some embodiments, the number of memory buffer interfaces 360 may be configured to match the number of memory buffers 240 and processing engines 350, and hence, the number of sample paths 230. By implementing parallel memory buffer interfaces 360 for each memory buffer 240, processing engines 350 of vDSP 220 may read sample streams from memory buffers 240, concurrently. For example, enginel 350-1 may read IQ sample stream data from Meml 240-1, engine2350-2 may read IQ sample stream data from Mem2240-2, engine3 350-3 may read digital Tx sample stream data from Mem3 240-3, and engine4 350-4 may read IQ sample stream data from Mem4 240-4, concurrently. [0057] At 408, the apparatus may perform parallel processing of the plurality of sample streams to calibrate the plurality of sample paths. For example, referring to FIG. 3, by implementing parallel processing engines 350, vDSP 220 may perform parallel processing of the sample streams to calibrate various aspects of RF chip 204 (e.g., sample paths 230) concurrently. For example, enginel 3501 may calibrate the Rxl sample path 230-1, while engine2 350-2 concurrently calibrates the Rx2 sample path 230-2. In some embodiments, enginel 350-1 may calibrate the Rxl sample path 230-1, while engine3 350-3 concurrently calibrates the Txl sample path 230-3. In some embodiments, if the TAR1 sample path 230-4 is used to calibrate the Txl sample path 230-3, TAR1 sample path 230-4 may stream Txl samples via coupler 310. In some embodiments, enginel 350-1, engine2 350-2, and engine3 350-3 may concurrently calibrate the Rxl sample path 230-1, the Rx2 sample path 230-2, and the Txl sample path 230-3, respectively. [0058] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0059] According to one aspect of the present disclosure, an RF chip is provided. The RF chip may include a plurality of sample paths configured to generate a plurality of sample streams. The RF chip may include a plurality of memory buffers coupled to the plurality of sample paths and configured to receive the plurality of sample streams. The RF chip may include a vDSP. The vDSP may be configured to read the plurality of sample streams from the plurality of memory buffers, concurrently. The vDSP may be configured to perform parallel processing of the plurality of sample streams to calibrate the plurality of sample paths.

[0060] In some embodiments, the vDSP may include a plurality of processing engines configured to perform the parallel processing of the plurality of sample streams.

[0061] In some embodiments, each of the plurality of processing engines may be associated with one of the plurality of sample paths.

[0062] In some embodiments, the vDSP may include a plurality of memory interfaces configured to interface with the plurality of memory buffers.

[0063] In some embodiments, the plurality of sample paths comprise one or more of at least one Rx sample path, at least one Tx sample path, or at least one TAR sample path.

[0064] In some embodiments, the at least one Rx sample path may be configured to generate at least one first IQ sample stream. In some embodiments, the at least one Tx sample path may be configured to generate at least one digital Tx sample stream. In some embodiments, the at least one TAR sample path may be configured to generate at least one second IQ sample stream.

[0065] In some embodiments, the parallel processing may be associated with a plurality of calibration procedures. In some embodiments, the plurality of calibration procedures comprise one or more of an Rx gain calibration procedure, an IQ mismatch calibration procedure, a PA calibration procedure, a Tx IIP2 calibration procedure, a Tx power calibration procedure, or antenna tuning.

[0066] In some embodiments, each of the plurality of memory buffers may be configured for concurrent write and read operations by an associated sample path and the vDSP, respectively. [0067] In some embodiments, the plurality of memory buffers may include a plurality of dual port memories. In some embodiments, the plurality of buffers may include a plurality of ping- pong buffers.

[0068] According to another aspect of the present disclosure, a vDSP of an RF chip is provided. The vDSP may include a plurality of memory interfaces configured to interface with a plurality of memory buffers associated with a plurality of sample paths. The vDSP may include a plurality of processing engines coupled to the plurality of memory interfaces. The plurality of processing engines may be configured to read, via the plurality of memory interfaces, a plurality of sample streams from the plurality of memory buffers concurrently, the plurality of sample streams being associated with the plurality of sample paths. The plurality of processing engines may be configured to perform parallel processing of the plurality of sample streams to calibrate the plurality of sample paths.

[0069] In some embodiments, each of the plurality of processing engines may be associated with one of the plurality of sample paths. [0070] In some embodiments, the plurality of memory interfaces may include one or more of a first subset of memory interfaces associated with at least one Rx sample buffer, a second subset of memory interfaces associated with at least one Tx sample buffer, and a third subset of memory interfaces associated with at least one TAR sample buffer.

[0071] In some embodiments, the plurality of processing engines may be configured to read the plurality of sample streams from the plurality of memory buffers concurrently by reading, via the first subset of memory interfaces, at least one first IQ sample stream from the at least one Rx sample buffer.

[0072] In some embodiments, the plurality of processing engines may be configured to read the plurality of sample streams from the plurality of memory buffers concurrently by reading, via the second subset of memory interfaces, at least one digital Tx sample stream from the at least one Tx sample buffer.

[0073] In some embodiments, the plurality of processing engines may be configured to read the plurality of sample streams from the plurality of memory buffers concurrently by reading, via the third subset of memory interfaces, at least one second IQ sample stream from the at least one TAR sample buffer.

[0074] In some embodiments, the parallel processing may be associated with a plurality of calibration procedures. In some embodiments, the plurality of calibration procedures comprise one or more of an Rx gain calibration procedure, an IQ mismatch calibration procedure, a PA calibration procedure, a Tx IIP2 calibration procedure, a Tx power calibration procedure, or antenna tuning.

[0075] According to yet another aspect of the present disclosure, a method of wireless communication of an RF chip is provided. The method may include generating, by a plurality of sample paths, a plurality of sample streams. The method may include receiving, by a plurality of memory buffers, the plurality of sample streams concurrently. The method may include reading, by a vDSP, the plurality of sample streams from the plurality of memory buffers concurrently. The method may include performing, by the vDSP, parallel processing of the plurality of sample streams to calibrate the plurality of sample paths.

[0076] In some embodiments, the generating the plurality of sample streams may include generating, by at least one Rx sample path, at least one first IQ sample stream. In some embodiments, the generating the plurality of sample streams may include generating, by at least one Tx sample path, at least one digital Tx sample stream. In some embodiments, the generating the plurality of sample streams may include generating, by at least one TAR sample path, at least one second IQ sample stream.

[0077] In some embodiments, the performing the parallel processing of the plurality of sample streams may include performing a plurality of calibration procedures concurrently. In some embodiments, the plurality of calibration procedures may include one or more of an Rx gain calibration procedure, an IQ mismatch calibration procedure, a PA calibration procedure, a Tx IIP2 calibration procedure, a Tx power calibration procedure, or antenna tuning.

[0078] The foregoing description of the embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0079] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0080] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0081] Various functional blocks, modules, and steps are disclosed above. The arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0082] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.