BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modem terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various mechanisms for calibrating an envelope tracking (ET) path and an in-phase/in-quadrature (IQ) path of a radio frequency (RF) chip.

SUMMARY

[0003] Embodiments of apparatus and method of wireless communication are disclosed herein.

[0004] According to one aspect of the present disclosure, an RF chip is provided. The RF chip may include a waveform generator. The waveform generator may be configured to generate a calibration waveform and a constant waveform of a same length. The waveform generator may be configured to input, at a beginning of a first period, the calibration waveform into an IQ path and the constant waveform into an ET path. The waveform generator may be configured to input, at a beginning of a second period, the calibration waveform into the ET path and the constant waveform into the IQ path. The first period and the second period may be contiguous in a time domain. The RF chip may include a correlation circuit. The correlation circuit may be configured to obtain, from a power amplifier (PA), a first set of correlation samples associated with the first period and a second set of correlation samples associated with the second period. The correlation circuit may be configured to estimate a delay difference between the IQ path and the ET path based on the first set of correlation samples associated with the first period and the second set of correlation samples associated with the second period. [0005] According to another aspect of the disclosure, an apparatus for wireless communication is provided. The apparatus may include an RF chip. The RF chip may include a waveform generator. The waveform generator may be configured to generate a calibration waveform and a constant waveform of a same length. The waveform generator may be configured to input, at a beginning of a first period, the calibration waveform into an IQ path and the constant waveform into an ET path. The IQ path and the ET path may be associated with an RF chip. The waveform generator may be configured to input, at a beginning of a second period, the calibration waveform into the ET path and the constant waveform into the IQ path, the first period and the second period being contiguous in a time domain. The apparatus may include a correlation circuit. The correlation circuit may be configured to obtain, from a PA, a first set of correlation samples associated with the first period and a second set of correlation samples associated with the second period. The correlation circuit may be configured to estimate a delay difference between the IQ path and the ET path based on the first set of correlation samples associated with the first period and the second set of correlation samples associated with the second period.

[0006] According to yet another aspect of the disclosure, a method of wireless communication is provided. The method may include generating, by a waveform generator, a calibration waveform and a constant waveform of a same length. The method may include inputting, by the waveform generator, the calibration waveform into an IQ path and the constant waveform into an ET path at a beginning of a first period, the IQ path and the ET path being associated with a RF chip. The method may include inputting, by the waveform generator, the calibration waveform into the ET path and the constant waveform into the IQ path at a beginning of a second period, the first period and the second period being contiguous in a time domain. The method may include obtaining, by a correlation circuit, a first set of correlation samples associated with the first period and a second set of correlation samples associated with the second period from a PA. The method may include estimating, by the correlation circuit, a delay difference between the IQ path and the ET path based on the first set of correlation samples associated with the first period and the second set of correlation samples associated with the second period.

[0007] These illustrative embodiments are mentioned not to limit or define the disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0009] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0010] FIG. 2 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0011] FIG. 3 A illustrates a detailed block diagram of the RF chip of FIG. 2 depicting an ET path, an IQ path, and a transmit (Tx) auxiliary receive (TAR) path, according to some embodiments of the present disclosure.

[0012] FIG. 3B illustrates a graphical representation of a calibration waveform and a constant waveform that may be used to calibrate the ET path and the IQ path of the RF chip depicted in FIG. 2, according to some embodiments of the present disclosure.

[0013] FIG. 4 illustrates a flow chart of an exemplary method of wireless communication, according to some embodiments of the present disclosure.

[0014] FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0015] FIG. 6 illustrates a conventional RF chip.

[0016] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0017] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0018] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0019] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0020] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system.

[0021] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0022] In the marketplace today, there are a wide variety of electronic devices available for a wide variety of purposes. Such devices include cellular telephones, tablet computers, laptop computers, personal computers, intemet-of-things (loT) devices, smart vehicles, smart devices, televisions, Bluetooth™ enabled devices, printers, and cameras, just to name a few. It is often desirable for one electronic device to communicate with one or more other electronic devices. To facilitate these communications, various wireless technologies have become popular. Regardless of the particular type of wireless communication technology, these technologies are all similar in the sense that they use radio waves, often referred to as radio-frequency (RF) signals, to communicate information from one device to another.

[0023] Information to be transmitted is typically modulated onto the RF signal prior to transmission to a receiving device. In other words, the information is typically embedded in an envelope of a carrier signal that has a frequency in the RF range. The envelope is typically referred to as the baseband signal or IQ signal, and there are various techniques for using IQ signals to modulate the carrier signal. The receiving device demodulates a received signal by removing the carrier signal to recover the information embedded in the envelope. ET describes an approach to RF amplifier design in which the power supply voltage applied to the RF chip’s PA is continuously adjusted to ensure that the PA is operating at peak power efficiency at each instant during a transmission. An example of a conventional RF chip that performs ET is depicted in FIG. 6.

[0024] FIG. 6 illustrates a conventional RF chip 600 (referred to hereinafter as “RF chip 600). As shown in FIG. 6, RF chip 600 includes an ET path 601, and an IQ path 603. ET path 601 includes an ET detrough 602, an envelope (ENV) digital-to-analog converter (DAC) 604, and an ENV tracker 606. IQ path 603 includes a digital pre-distortion (DPD) circuit 608, an IQ DAC 610, an analog baseline filter 612, and a PA 614 coupled to antenna 618.

[0025] As shown in FIG. 6, an IQ signal generated by a baseband chip (not shown) may be input into ET path 601 and IQ path 603. ET tracking along ET path 601 may include identifying an envelope shaping detrough function from a shaping table at ET detrough 602, digital-to-analog (DAC) conversion by ENV DAC 604, and amplification of the output of the ENV DAC 604 by ENV tracker 606. The amplification by ENV tracker 606 may be used to modulate the supply voltage applied to PA 614 to provide peak power efficiency.

[0026] Since the IQ signal is split into ET path 601 and IQ path 603, and then combined at PA 614, the delay matching between these two paths is critical to achieve good performance. In other words, PA 614 must align the modulated supply voltage and the RF input signal in the time domain with a high degree of accuracy. Even small time deviations in the nanosecond (ns) range may substantially degrade the quality of the RF output signal. This is especially detrimental to wideband RF signals, which are particularly sensitive to this type of deviation.

[0027] ET path 601 and IQ path 603 may have different delays for various reasons. For example, the digital circuits of these two paths may not be the same. In other words, ET path 601 and IQ path 603 may have a different number of processing circuits. Moreover, ENV DAC 604 and IQ DAC 610 may have different delays. Still further, analog baseline filter 612 of IQ path 603 is absent from ET path 601, thereby introducing a delay in IQ path 603 that is absent from ET path 601. Thus, ET path 601 and IQ path 603 should be calibrated to avoid a misalignment of the modulated supply voltage and the RF input signal at PA 614.

[0028] Conventional techniques for calibrating ET path 601 and IQ path 603 include, e.g., slow ET delay calibration. Using slow ET delay calibration, the delays between ET path 601 and IQ path 603 are swept, and performance metric(s) such as power added efficiency (PAE), error vector magnitude (EVM), and/or adjacent channel leakage ratio (ACER) measured. Then, optimal delay is found when the best performance is achieved based on an evaluation of the performance metric(s). However, identifying a delay between ET path 601 based on a swept and performance metric evaluation is a time consuming process, which degrades system performance.

[0029] Thus, there exists an unmet need for a technique for calibrating the ET and IQ paths at an RF chip that uses a reduced amount of time and increases the accuracy of the calibration.

[0030] To overcome these and other challenges, the present disclosure provides a fast ET calibration technique that calibrates the ET and IQ paths of an RF chip with a reduced amount of time and a higher degree of accuracy, as compared with known techniques. For example, the fast ET calibration technique may be achieved by simultaneously injecting a calibration waveform (e.g., a wideband, fast-changing waveform) and a constant waveform of the same length into the IQ path and the ET path, respectively, at the beginning of a first period L. Then, at the beginning of a new period L, the injection of the waveforms switches such that the calibration waveform is injected into the ET path, and the constant waveform is injected into the IQ path. During each period, the PA combines the calibration waveform and the constant waveform to generate a set of correlation samples. After a predetermined number of periods (two or more), a correlation circuit (either a transmit auxiliary receiver (TAR) path of the RF chip or an external analyzer, such as a vector signal analyzer (VS A)) coupled to the PA compares the different sets of correlation samples generated by the PA. In the time domain, the correlation circuit will observe variations between the combined signals of different periods. Based on the variations, the correlation circuit may estimate a delay offset between the ET path and the IQ path, which may be used to calibrate the PA. This technique may be performed periodically such that the PA combines the power voltage supply signal from the ET path and the RF input signal in the time domain with a high degree of precision. Additional details of the fast ET calibration technique are provided below in connection with FIGs. 1-5.

[0031] FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0032] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0033] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0034] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides quality-of-service (QoS) flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0035] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node. [0036] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0037] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG. 5. Node 500 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 500 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 106. Other implementations are also possible. [0038] Transceiver 506 may include any suitable device for sending and/or receiving data. Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0039] As shown in FIG. 5, node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included. Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 502 may be a hardware device having one or more processing cores. Processor 502 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0040] As shown in FIG. 5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage. For example, memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502. Broadly, memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0041] Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions. In some embodiments, processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 502 and transceiver 506 (and memory 504 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0042] Referring back to FIG. 1, in some embodiments, user equipment 102 may implement a fast ET calibration technique that calibrates the ET and IQ paths of an RF chip with a reduced amount of time and a higher degree of accuracy, as compared with known techniques. For example, the fast ET calibration technique may be achieved by simultaneously injecting a calibration waveform (e.g., a wideband, fast-changing waveform) and a constant waveform of the same length into the IQ path and the ET path, respectively, at the beginning of a first period L. Then, at the beginning of a new period L, the injection of the waveforms switches such that the calibration waveform is injected into the ET path, and the constant waveform is injected into the IQ path. During each period, the PA combines the calibration waveform and the constant waveform to generate a set of correlation samples. After a predetermined number of periods (two or more), a correlation circuit (either a TAR path of the RF chip or an external analyzer, such as a VS A) coupled to the PA compares the different sets of correlation samples generated by the PA. In the time domain, the correlation circuit will observe variations between the combined signals of different periods. Based on the variations, the correlation circuit may estimate a delay offset between the ET path and the IQ path, which may be used to calibrate the PA. This technique may be performed periodically such that the PA combines the power voltage supply signal from the ET path and the RF input signal in the time domain with a high degree of precision. Additional details of the fast ET calibration technique are provided below in connection with FIGs. 2-5.

[0043] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip 202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be implemented as user equipment 102 of wireless network 100 in FIG. 1. As shown in FIG. 2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG. 5. Besides the on-chip memory 218 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG. 2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.

[0044] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Interface 214 of baseband chip 202 may receive the data from host chip 206. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In some embodiments, baseband chip 202 may include baseband circuit(s) 220, which may include a VS A. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204 via interface 214. RF chip 204, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital predistortion, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 204.

[0045] In the downlink, antenna 210 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202.

[0046] Although not shown in FIG. 2, RF chip 204 may include an ET path, an IQ path, a TAR path, and a waveform generator. The ET path may be used for envelope tracking of an IQ signal generated by baseband chip 202. The IQ path may be used to convert the IQ signal to an RF signal. RF chip 204 may implement a fast ET calibration technique that calibrates the ET and IQ paths with a reduced amount of time and a higher degree of accuracy, as compared with known techniques. For example, the fast ET calibration technique may be achieved by simultaneously injecting (by the waveform generator) a calibration waveform (e.g., a wideband, fast-changing waveform) and a constant waveform of the same length into the IQ path and the ET path, respectively, at the beginning of a first period L. Then, at the beginning of a new period L, the waveform generator may switch the injection of the waveforms such that the calibration waveform is injected into the ET path and the constant waveform is injected into the IQ path. During each period, the PA of the IQ path combines the calibration waveform and the constant waveform to generate a set of correlation samples. After a predetermined number of periods (two or more), a correlation circuit (either a TAR path of the RF chip or an external analyzer, such as a VSA of baseband circuits 220) coupled to the PA compares the different sets of correlation samples generated by the PA. In the time domain, the correlation circuit will observe variations between the combined signals of different periods. Based on the variations, the correlation circuit may estimate a delay offset between the ET path and the IQ path, which may be used to calibrate the PA. This technique may be performed periodically such that the PA combines the power voltage supply signal from the ET path and the RF input signal in the time domain with a high degree of precision. Additional details of the fast ET calibration technique are provided below in connection with FIGs. 3 A, 3B, and 4.

[0047] FIG. 3 A illustrates a detailed block diagram of the RF chip 204 of FIG. 2 depicting an ET path 301, an IQ path 303, and a TAR path 305, according to some embodiments of the present disclosure. FIG. 3B illustrates a graphical representation 300 of a calibration waveform and a constant waveform that may be used to calibrate the ET path 301 and the IQ path 303 of the RF chip 204 depicted in FIG. 3 A, according to some embodiments of the present disclosure. FIGs. 3 A and 3B will be described together.

[0048] Referring to FIG. 3 A, ET path 301 includes an ET detrough 302, an ENV DAC 304, and an ENV tracker 306. IQ path 303 includes a DPD circuit 308, an IQ DAC 310, an analog baseline filter 312, and a PA 314 coupled to antenna 210. TAR path 305 may include a correlation circuit 316 configured to estimate a delay between ET path 301 and IQ path 303. Moreover, referring to FIGs. 3 A and 3B, waveform generator 320 may include a constant waveform generator 330 configured to generate a constant waveform 325, a calibration waveform generator 340 configured to generate a calibration waveform 315, and a sample counter 350 configured to determine the start of a new period L and switch the path (ET path 301 or IQ path 303) into which the calibration waveform 315 and the constant waveform 325 are injected. As mentioned above, calibration waveform 315 may include a wideband, fast varying waveform. In some embodiments, the calibration waveform 315 may be injected into both IQ path 303 and ET paths 301. In some embodiments, constant waveform 325 may be generated by overwriting calibration waveform 315 with a constant controlled by a control register (not shown) of waveform generator 320.

[0049] As mentioned above, since the IQ signal (not shown in FIG. 3A) is split into ET path 301 and IQ path 303, and then combined at PA 314, the delay matching between these two paths is critical to achieve good performance. In other words, PA 314 must align the modulated supply voltage and the RF input signal in the time domain with a high degree of accuracy. Even small time deviations in the nanosecond (ns) range may substantially degrade the quality of the RF output signal. This is especially detrimental to wideband RF signals, which are particularly sensitive to this type of deviation. ET path 301 and IQ path 303 may have different delays for various reasons. For example, the digital circuits of these two paths may not be the same. In other words, ET path 301 and IQ path 303 may have a different number of processing circuits. Moreover, ENV DAC 304 and IQ DAC 310 may have different delays. Still further, analog baseline filter 312 of IQ path 303 is absent from ET path 301, thereby introducing a delay in IQ path 303 that is absent from ET path 301. Thus, ET path 301 and IQ path 303 may be calibrated to avoid a misalignment of the modulated supply voltage and the RF input signal at PA 614. To avoid these types of deviations and to perform calibration in a reduced amount of time, RF chip 204 may implement the fast ET calibration.

[0050] For example, during each period, PA 314 may combine the calibration waveform 315 and the constant waveform 325 to generate a set of correlation samples. After a predetermined number of periods (two or more), correlation circuit 316 of TAR path 305 (or an external analyzer, such as a VSA of baseband circuits 220) may compare the different sets of correlation samples generated by PA 314. In the time domain, correlation circuit 316 may observe variations that correspond to a delay mismatch 335 between the combined signals of different periods. Delay mismatch 335 may correspond to a delay difference between ET path 301 and the IQ path 303. Once identified/estimated, delay mismatch 335 may be used to calibrate PA 314. This technique may be performed periodically such that PA 314 aligns the power voltage supply signal from ET path 301 and the RF input signal of IQ path 303 in the time domain with sub-nanosecond-level precision.

[0051] FIG. 4 illustrates a flowchart of an exemplary method 400 of wireless communication, according to embodiments of the disclosure. Exemplary method 400 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, RF chip 204, waveform generator 320, ET path 301, IQ path 303, TAR path 305, correlation circuit 316, PA 314, baseband circuits(s) 220, and/or node 500. Method 400 may include steps 402-412 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4.

[0052] Referring to FIG. 4, at 402, the apparatus may generate a calibration waveform and a constant waveform of a same length. For example, referring to FIGs. 3A and 3B, calibration waveform generator 340 may generate calibration waveform 315, and constant waveform generator 330 may generate constant waveform 325. In some embodiments, the calibration waveform 315 may be injected into both IQ path 303 and ET paths 301. In some embodiments, constant waveform 325 may be generated by overwriting calibration waveform 315 with a constant controlled by a control register of waveform generator 320.

[0053] At 404, the apparatus may input the calibration waveform into an IQ path and the constant waveform into an ET path at a beginning of a first period. For example, referring to FIGs. 3 A and 3B, waveform generator 320 may input calibration waveform 315 into IQ path 303 and constant waveform 325 into ET path 301 at the beginning of a period. In the example illustrated in FIG. 3B, this period may include period 2L.

[0054] At 406, the apparatus may input the calibration waveform into the ET path and the constant waveform into the IQ path at a beginning of a second period, the first period and the second period being contiguous in a time domain. For example, referring to FIGs. 3A and 3B, waveform generator 320 may input calibration waveform 315 into ET path 301 and constant waveform 325 into IQ path 303 at the beginning of a new period. In the example illustrated in FIG. 3B, this new period may include period 2L.

[0055] At 408, the apparatus may obtain a first set of correlation samples associated with the first period and a second set of correlation samples associated with the second period from a PA. For example, referring to FIG. 3 A, for each period, correlation circuit 316 may obtain a set of correlation samples associated with a combined signal of calibration waveform 315 and constant waveform 325 from PA 314.

[0056] At 410, the apparatus may estimate a delay difference between the IQ path and the ET path based on the first set of correlation samples associated with the first period and the second set of correlation samples associated with the second period. For example, referring to FIGs. 3A and 3B, correlation circuit 316 may observe variations in the time-domain that corresponds to a delay mismatch 335 between the combined signals of different periods. Delay mismatch 335 may correspond to a delay difference between ET path 301 and the IQ path 303.

[0057] At 412, the apparatus may calibrate the IQ path and the ET path based on the delay difference. For example, referring to FIGs. 3 A and 3B, once identified/estimated, delay mismatch 335 may be used to calibrate ET path 301 and IQ path 303 at PA 314. This technique may be performed periodically such that PA 314 aligns the power voltage supply signal from ET path 301 and the RF input signal of IQ path 303 in the time domain with sub-nanosecond-level precision.

[0058] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0059] According to one aspect of the present disclosure, an RF chip is provided. The RF chip may include a waveform generator. The waveform generator may be configured to generate a calibration waveform and a constant waveform of a same length. The waveform generator may be configured to input, at a beginning of a first period, the calibration waveform into an IQ path and the constant waveform into an ET path. The waveform generator may be configured to input, at a beginning of a second period, the calibration waveform into the ET path and the constant waveform into the IQ path. The first period and the second period may be contiguous in a time domain. The RF chip may include a correlation circuit. The correlation circuit may be configured to obtain, from a PA, a first set of correlation samples associated with the first period and a second set of correlation samples associated with the second period. The correlation circuit may be configured to estimate a delay difference between the IQ path and the ET path based on the first set of correlation samples associated with the first period and the second set of correlation samples associated with the second period.

[0060] In some embodiments, the correlation circuit may be further configured to calibrate the IQ path and the ET path based on the delay difference.

[0061] In some embodiments, the calibration waveform and the constant waveform may repeat in the first period and the second period.

[0062] In some embodiments, the calibration waveform may be injected into both IQ path and ET paths. In some embodiments, the constant waveform may be generated by overwriting the calibration waveform with a constant controlled by a control register.

[0063] In some embodiments, the RF chip may further include the PA. In some embodiments, the PA may be configured to combine, during the first period, the calibration waveform input into the IQ path and the constant waveform input into the ET path to generate a first combined signal. In some embodiments, the PA may be configured to combine, during the second period, the constant waveform input into the IQ path and the calibration waveform input into the ET path to generate a second combined signal. In some embodiments, the first set of correlation samples may be associated with the first combined signal. In some embodiments, the second set of correlation samples may be associated with the second combined signal.

[0064] In some embodiments, the correlation circuit may be associated with a TAR path.

[0065] According to another aspect of the disclosure, an apparatus for wireless communication is provided. The apparatus may include an RF chip. The RF chip may include a waveform generator. The waveform generator may be configured to generate a calibration waveform and a constant waveform of a same length. The waveform generator may be configured to input, at a beginning of a first period, the calibration waveform into an IQ path and the constant waveform into an ET path. The IQ path and the ET path may be associated with an RF chip. The waveform generator may be configured to input, at a beginning of a second period, the calibration waveform into the ET path and the constant waveform into the IQ path, the first period and the second period being contiguous in a time domain. The apparatus may include a correlation circuit. The correlation circuit may be configured to obtain, from a PA, a first set of correlation samples associated with the first period and a second set of correlation samples associated with the second period. The correlation circuit may be configured to estimate a delay difference between the IQ path and the ET path based on the first set of correlation samples associated with the first period and the second set of correlation samples associated with the second period.

[0066] In some embodiments, the correlation circuit may be further configured to calibrate the IQ path and the ET path based on the delay difference.

[0067] In some embodiments, the calibration waveform and the constant waveform may repeat in the first period and the second period.

[0068] In some embodiments, the calibration waveform may be injected into both IQ path and ET paths. In some embodiments, the constant waveform may be generated by overwriting the calibration waveform with a constant controlled by a control register.

[0069] In some embodiments, RF chip may include the PA.

[0070] In some embodiments, the PA may be configured to combine, during the first period, the calibration waveform input into the IQ path and the constant waveform input into the ET path to generate a first combined signal. In some embodiments, the PA may be configured to combine, during the second period, the constant waveform input into the IQ path and the calibration waveform input into the ET path to generate a second combined signal. In some embodiments, the first set of correlation samples may be associated with the first combined signal. In some embodiments, the second set of correlation samples may be associated with the second combined signal.

[0071] In some embodiments, the RF chip may include the correlation circuit.

[0072] In some embodiments, the correlation circuit may be associated with a TAR path of the RF chip.

[0073] In some embodiments, the correlation circuit may be external to the RF chip. [0074] In some embodiments, the correlation circuit may include a VS A.

[0075] According to yet another aspect of the disclosure, a method of wireless communication is provided. The method may include generating, by a waveform generator, a calibration waveform, and a constant waveform of a same length. The method may include inputting, by the waveform generator, the calibration waveform into an IQ path and the constant waveform into an ET path at a beginning of a first period, the IQ path and the ET path being associated with an RF chip. The method may include inputting, by the waveform generator, the calibration waveform into the ET path and the constant waveform into the IQ path at a beginning of a second period, the first period, and the second period being contiguous in a time domain. The method may include obtaining, by a correlation circuit, a first set of correlation samples associated with the first period and a second set of correlation samples associated with the second period from a PA. The method may include estimating, by the correlation circuit, a delay difference between the IQ path and the ET path based on the first set of correlation samples associated with the first period and the second set of correlation samples associated with the second period.

[0076] In some embodiments, the method may include calibrating, by the correlation circuit, the IQ path and the ET path based on the delay difference.

[0077] In some embodiments, the calibration waveform and the constant waveform may repeat in the first period and the second period.

[0078] In some embodiments, the calibration waveform may be injected into both IQ path and ET paths. In some embodiments, the constant waveform may be generated by overwriting the calibration waveform with a constant controlled by a control register.

[0079] In some embodiments, the method may include combining, by the PA during the first period, the calibration waveform input into the IQ path and the constant waveform input into the ET path to generate a first combined signal. In some embodiments, the method may include combining, by the PA during the second period, the constant waveform input into the IQ path and the calibration waveform input into the ET path to generate a second combined signal. In some embodiments, the first set of correlation samples may be associated with the first combined signal. In some embodiments, the second set of correlation samples may be associated with the second combined signal.

[0080] In some embodiments, the correlation circuit may be associated with a TAR path of the RF chip.

[0081] In some embodiments, the correlation circuit may include a VS A external to the RF chip.

[0082] The foregoing description of the embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0083] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0084] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0085] Various functional blocks, modules, and steps are disclosed above. The arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0086] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.