ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING, SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH SAME, DESIGN METHOD THEREOF, AND TEST PATTERN GENERATION METHOD

Title:

ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING, SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH SAME, DESIGN METHOD THEREOF, AND TEST PATTERN GENERATION METHOD

Document Type and Number:

WIPO Patent Application WO/2011/158500

Kind Code:

A1

Abstract:

The disclosed asynchronous memory element for scanning is provided with an n-input asynchronous memory element (12), and a scan control logic circuit (14) that generates the n-input for the asynchronous memory element (12) from an n-bit signal input and scan input. The scan control logic circuit (14) outputs, as the n-input for each asynchronous memory element (12), a signal input when the control signal applied is a first bit pattern, a scan input when the signal is a second bit pattern, and a bit pattern where the asynchronous memory element (12) retains a previous value at all other times.

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Inventors:

OHTAKE SATOSHI (JP)
IWATA HIROSHI (JP)
INOUE MICHIKO (JP)

Application Number:

PCT/JP2011/003405

Publication Date:

December 22, 2011

Filing Date:

June 15, 2011

Export Citation:

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Assignee:

NAT UNIV CORP NARA INST (JP)
OHTAKE SATOSHI (JP)
IWATA HIROSHI (JP)
INOUE MICHIKO (JP)

International Classes:

G01R31/28; G06F11/22; H03K19/00

Foreign References:

JPH07202645A	1995-08-04
JP2004521352A	2004-07-15

Other References:

FRANK TE BEEST ET AL.: "A Multiplexer Based Test Method for Self-Timed Circuits", PROCEEDINGS OF THE LLTH IEEE INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2005, pages 166 - 175
ALEX KONDRATYEV ET AL.: "Testing of Asynchronous Designs by "Inappropriate" Means. Synchronous approach", PROCEEDINGS OF THE EIGHTH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2002, pages 171 - 180

Attorney, Agent or Firm:

MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)

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