Title:
ASYNCHRONOUS SAR ADC USING TWO-STAGE COMPARATOR HAVING SEPARATE RESETS
Document Type and Number:
WIPO Patent Application WO/2022/089226
Kind Code:
A1
Abstract:
Systems and circuits for an asynchronous SAR ADC (300) are described. The SAR ADC (300) includes a two-stage comparator (320) with a preamplifier first stage (322) and a latch second stage (324). The preamplifier first stage (322) is activated by an active pulse of a first clock signal (CLK1B) and the latch second stage (324) is activated by an active pulse of a second clock signal (CLK2). The Done signal from a done detector (340) is fed back as the active pulse of the first clock signal (CLK1B). The leading edge of the active pulse of the second clock signal (CLK2) is driven by the leading edge of the active pulse of the first clock signal (CLK1B) via an RS latch (342).
Inventors:
LEBEDEV SEMYON (CA)
ZAMANLOOY BABAK (CA)
LACROIX MARC-ANDRE (CA)
ZAMANLOOY BABAK (CA)
LACROIX MARC-ANDRE (CA)
Application Number:
PCT/CN2021/124157
Publication Date:
May 05, 2022
Filing Date:
October 15, 2021
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03M1/46; H03M1/12
Foreign References:
| US11133812B1 | 2021-09-28 | |||
| CN109995371A | 2019-07-09 | |||
| US20140070971A1 | 2014-03-13 | |||
| CN108736890A | 2018-11-02 | |||
| CN110249534A | 2019-09-17 | |||
| CN110546887A | 2019-12-06 | |||
| CN106537786A | 2017-03-22 |
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