I/O OPERATION OVER A BUS INTERFACE

BACKGROUND

Field

[0001] Embodiments relate to the asynchronous update of metadata tracks in response to a cache hit generated via an I/O operation over a bus interface.

Background

[0002] In certain storage system environments, a storage controller (or a storage controller complex) may comprise a plurality of storage servers that are coupled to each other. The storage controller allows host computing systems to perform input/output (I/O) operations with storage devices controlled by the storage controller, where the host computing systems may be referred to as hosts. In certain situations, the storage servers of the storage controller may each include a plurality of central processing units (CPU) that may be used to perform parallel execution of a plurality of tasks.

[0003] The storage controller may include a cache. Data written from a host may be stored in the cache and at an opportune time the data stored in the cache may be destaged (i.e., moved or copied) to a storage device. Data may also be staged (i.e., moved or copied) from a storage device to the cache of the storage controller. The storage controller may respond to a read I/O request from the host from the cache, if the data for the read I/O request is available in the cache, otherwise the data may be staged from a storage device to the cache for responding to the read I/O request. A write I/O request from the host causes the data corresponding to the write to be written to the cache, and then at an opportune time the written data may be destaged from the cache to a storage device. Since the storage capacity of the cache is relatively small in comparison to the storage capacity of the storage devices, data may be periodically destaged from the cache to create empty storage space in the cache. Data may be written and read from the cache much faster in comparison to reading and writing data from a storage device.

SUMMARY OF THE PREFERRED EMBODIMENTS

[0004] Provided are a method, a system, a storage controller, and a computer program product in which a cache hit is generated, in response to receiving an input/output (I/O) command over a bus interface. An update for a metadata track is stored in a buffer associated with a central processing unit (CPU) that processes the I/O command, in response to generating the cache hit. The metadata track is asynchronously updated from the buffer with the stored update for the metadata track in the buffer. As a result, the I/O command is preferably able to complete in a timely manner without waiting for the update to the metadata track.

[0005] In additional embodiments, the processing of the I/O command by the CPU is completed prior to asynchronously updating the metadata track from the buffer with the stored update for the metadata track in the buffer. As a result, the I/O command may complete in a timely manner, prior to the corresponding update to the metadata track being made.

[0006] In further embodiments, the buffer is a free buffer reserved for the CPU from a buffer pool. In response to the buffer being filled up with updates for metadata tracks by the CPU, the buffer is returned to the buffer pool. An indication is made to indicate that the buffer returned to the buffer pool is a used buffer. As a result, the used buffer may temporarily store updates for metadata tracks.

[0007] In certain embodiments, a background task of a plurality of background tasks performs operations for asynchronously updating the metadata track. As a result, updates to metadata tracks are made by tasks that execute in the background and does not hinder the processing of syncio operations.

[0008] In further embodiments, an indication is made to indicate that the used buffer is a free buffer, in response to asynchronously updating the metadata track from the used buffer with the stored update for the metadata track in the used buffer. As a result, used buffers are freed in a buffer pool and may be reused, when metadata updates have been completed from the used buffers.

[0009] In certain embodiments, a plurality of CPUs process a plurality of I/O commands over a plurality of bus interfaces. An adjustment is made of the number of the plurality of background tasks to maintain an adequate number of free buffers in the buffer pool, where the adequate number of free buffers in the buffer pool is greater than a first threshold number and fewer than a second threshold number. As a result, the number of free buffers and used buffers are kept in balance in the buffer pool.

[0010] In further embodiments, a plurality of an adjustable number of background tasks asynchronously updates a plurality of metadata tracks from a plurality of buffers with stored updates for the plurality of metadata tracks, where the stored updates for the plurality of metadata tracks in the plurality of buffers are generated by a plurality of CPUs. As a result of the background tasks being adjustable in number, the number of free buffers and used buffers are kept in balance in a buffer pool. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Preferred embodiments of the present invention will now be described by way of example, with reference to the following drawings (like reference numbers represent corresponding parts throughout):

FIG. 1 illustrates a block diagram of a computing environment comprising a storage controller coupled to one or more hosts and one or more storage devices for integrating syncio processing with cache and metadata management, in accordance with certain embodiments.

FIG. 2 illustrates a block diagram that shows the asynchronous update of metadata tracks in syncio, in accordance with certain embodiments;

FIG. 3 illustrates a block diagram that shows the reservation of free buffers from a buffer pool by CPUs, in accordance with certain embodiments;

FIG. 4 illustrates a flowchart that shows operations for managing the buffer pool, in accordance with certain embodiments;

FIG. 5 illustrates a flowchart that shows how a background task asynchronously updates metadata tracks, in accordance with certain embodiments;

FIG. 6 illustrates another flowchart that shows how a background task asynchronously updates metadata tracks, in accordance with certain embodiments;

FIG. 7 illustrates a flowchart that shows how the number of background tasks is adjusted to maintain an adequate number of free buffers in the buffer pool, in accordance with certain embodiments;

FIG. 8 illustrates a flowchart that shows how asynchronous updates of metadata tracks are made in response to a cache hit generated because of a syncio operation, in accordance with certain embodiments;

FIG. 9 illustrates a block diagram of a cloud computing environment, in accordance with certain embodiments; FIG. 10 illustrates a block diagram of further details of the cloud computing environment of FIG. 9, in accordance with certain embodiments; and

FIG. 11 illustrates a block diagram of a computational system that shows certain elements that may be included in the storage controller or the host, as described in FIGs. 1-10, in accordance with certain embodiments.

DETAILED DESCRIPTION

[0012] In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments. It is understood that other embodiments may be utilized and structural and operational changes may be made.

[0013] Syncio (also referred to as sync I/O) comprises an attachment hardware and protocol for computational devices. Syncio is designed for very low latency random reads and small block sequential writes. Syncio connections between computational devices may be over point to point optical Peripheral Component Interconnect Express (PCIe) interfaces. Syncio operations behave differently than traditional I/O in that in syncio a host computational device may hold an application thread in a spin loop while waiting for the I/O operation to complete. This avoids the need for processor cycles to perform the two context swaps of traditional I/O, the need to perform operations for putting the I/O thread to sleep and then re-dispatching the I/O thread, and the need for an I/O interrupt.

[0014] The code path for syncio needs to be extremely optimized to satisfy the time requirements for completion of syncio operations. Any condition that may delay the completion of a syncio operation may cause the storage controller to indicate to a host that the syncio operation cannot be completed, and the syncio operation may have to be retried from the host.

[0015] A syncio operation may cause a cache hit that may cause updates to be needed for one or metadata tracks, where a metadata track may store information regarding a plurality of tracks stored in the cache. For example, a metadata track may store information (metadata) regarding a thousand tracks stored in the cache. Direct update of the one or more metadata tracks may not be possible within the time period in which the syncio operation must complete, because a plurality of CPUs that may be performing syncio operations may need to write to the same metadata track and must take turns for writing to the same metadata track. Additionally, some of the metadata tracks may be on a disk storage device and it may not be possible to update such metadata tracks within the time period in which the syncio operation must complete.

[0016] Certain embodiments, update a plurality of buffers associated with a plurality of CPUs with the information (metadata) that is to be written to metadata tracks, when cache hits occur during syncio operations performed by the plurality of CPUs. The updates to the buffers associated with the CPUs can be completed within the time periods in which the syncio operations need to complete. Background tasks may update the metadata tracks with the metadata written to the buffers. Therefore, the update of the metadata tracks is performed asynchronously with the syncio operations, i.e., the update to a metadata track corresponding to a track need not be performed while a syncio operation performs an I/O operation on the track.

Exemplary Embodiments

[0017] FIG. 1 illustrates a block diagram of a computing environment 100 comprising a storage controller 102 coupled to one or more hosts 104, 106, and one or more storage devices 108, 110, in accordance with certain embodiments. The storage controller 102 allows the plurality of hosts 104, 106 to perform input/output (I/O) operations with logical storage maintained by the storage controller 102. The physical storage corresponding to the logical storage may be found in one or more of the storage devices 108, 110 and/or a cache 112 (e.g., a memory) of the storage controller 102.

[0018] The storage controller 102 and the hosts 104, 106 may comprise any suitable computational device including those presently known in the art, such as, a personal computer, a workstation, a server, a mainframe, a hand held computer, a palm top computer, a telephony device, a network appliance, a blade computer, a processing device, etc. The storage controller 102, the hosts 104, 106, and the storage devices 108, 110 may be elements in any suitable network 114, such as, a storage area network, a wide area network, the Internet, an intranet. In certain embodiments, the storage controller 102, the hosts 104, 106, and the storage devices 108, 110 may be elements in a cloud computing environment that comprises the computing environment 100. The storage devices 108, 110 may be comprised of storage disks, tape drives, solid state storage, etc., and may be controlled by the storage controller 102.

[0019] In certain embodiments, the hosts 104, 106 may be coupled to the storage controller 102 via a bus interface (e.g., a point to point optical PCIe interface) 116, 118 and a network interface 120, 122. Syncio operations from the hosts 104, 106 may be performed over the bus interfaces 116, 118. Traditional I/O operations from the hosts 104, 106 may be performed over the network interfaces 120, 122. The bus interfaces 116, 118 may comprise a faster access channel for I/O than the network interfaces 120, 122. Additional bus interface technology to extend the bus interface 116, 118 may be utilized, including PCIe extender cables or components, such as a distributed PCIe switch, to allow PCIe over Ethernet, such as with the ExpEther technology.

[0020] The cache 112 may store a plurality of tracks 124 that include customer data tracks, metadata tracks, and other tracks. Metadata tracks may also be stored in the storage devices 108, 110. Each of the metadata tracks may store information on one or more customer data tracks. Therefore, metadata 126 for a plurality of customer data tracks is stored in a plurality of metadata tracks 128, 130 where each metadata track stores information on customer data tracks of one or more customers and some or all of the metadata tracks 128, 130 may be present in the cache 112 and some of all of the metadata tracks 128. 130 may be present in one or more of the storage devices 108, 110.

[0021] The storage controller 102 executes one or more syncio processes 132, one or more background tasks 134, and a background task adjustment process 136. The syncio processes 132 may execute on a plurality of CPUs 138, 140 of the storage controller. A buffer pool 142 comprising one or more free buffers 144 and one or more used buffers 146 are maintained in the storage controller 102, where each of the buffers 144, 146 in the buffer pool 142 comprises memory that may be associated with a CPU of the plurality of CPUs 138, 140.

[0022] In certain embodiments, a CPU 138 may perform a syncio operation and because of cache hits to a track of the cache 112, the CPU 138 updates a previously reserved buffer selected from the free buffers 144 with information that needs to be written to metadata track 128 corresponding to the track of the cache 112. The background task 134 may update the metadata tracks 128, 130 asynchronously with the performing of syncio operations, by copying information written to a plurality of buffers by a plurality of CPUs 138, 140 during the syncio operations, to the metadata tracks (i.e., a syncio operation can complete before a metadata track is updated). A background task adjustment process 136 adjusts the number of background tasks to ensure that there is an adequate number of free buffers 144 that may be reserved by the CPUs 138, 140 to temporarily write the information that is ultimately to be written to the metadata tracks 128, 130.

[0023] FIG. 2 illustrates a block diagram 200 that shows the asynchronous update of metadata tracks in syncio, in accordance with certain embodiments. In certain embodiments, the operations shown in FIG. 2 may be performed by the storage controller 102.

[0024] Control starts at block 202 in which a cache hit on the cache 112 occurs during a syncio operation being performed by a CPU 138, and as a result an update to a metadata track 128 is needed. Direct update of metadata track 128 is not possible within the time period in which the syncio operation must complete because of any of the following reasons: (1) A plurality of CPUs 138, 140 may need to write on same metadata track 128 and the metadata track 128 may be already be locked for writing by another CPU besides the CPU 138; and (2) The metadata track 128 may be on a disk storage device and the time to write directly to the metadata track 128 or to write to a staged copy of the metadata track 128 exceeds the time within which the syncio operation is required to complete (as shown in block 204).

[0025] From block 202 control proceeds to block 206 in which the CPU 138 temporarily stores the update to be made to the metadata track in a buffer associated with the CPU 138. Additionally for a plurality of CPUs 138, 140 performing syncio operations (as shown via reference numeral 208) an adjustable number of background tasks 134 asynchronously update (at block 210) metadata tracks 128, 130 from the buffers in which the CPUs 138, 140 have written the updates to be made to the metadata tracks 128, 130.

[0026] FIG. 3 illustrates a block diagram 300 that shows the reservation of free buffers from a buffer pool 142 by CPUs 138, 140, in accordance with certain embodiments.

[0027] The buffer pool 142 may include a plurality of free buffers 302, 304 and a plurality of used buffers 306, 308. A free buffer is a buffer which is empty, i.e., the memory comprising the buffer may be written into without any data loss. A used buffer is a buffer that is full, i.e., more data may not be written to the memory comprising the buffer without overwriting already existing data that is needed by the storage controller 102.

[0028] In certain embodiments, when a CPU needs to update a metadata track and the CPU does not have any assigned buffer for exclusive writing by the CPU, the CPU reserves a free buffer of the buffer pool 142 and assigns the reserved free buffer for exclusive writing by the CPU. For example, in FIG. 3, CPU 138 has assigned itself the free buffer 310, and CPU 140 has assigned itself the free buffer 312. Since a buffer is a memory included in the storage controller 102, a CPU may write updates to a buffer that is reserved for the CPU much faster than to a metadata track, because the metadata track may be locked by another CPU or may be residing in a storage device.

[0029] FIG. 4 illustrates a flowchart 400 that shows operations for managing the buffer pool 142, in accordance with certain embodiments. In certain embodiments, the operations shown in FIG. 4 may be performed by the storage controller 102.

[0030] Control starts at block 402 in which the storage controller 102 maintains a buffer pool 142 comprising free buffers 144 and used buffers 146. A CPU 138 performs a syncio operation and if the CPU 138 does not have a reserved buffer then the CPU 138 reserves a free buffer for use by the CPU 138 from the buffer pool 142 (at block 404). If at block 404, the CPU 138 already has an existing reserved buffer that is not full, then the CPU 138 continues to the existing reserved buffer that is not full.

[0031] From block 404 control proceeds to block 406 in which a determination is made as to whether the CPU 138 needs to update a metadata track. For example, a metadata track may need to be updated if there is a read hit in the cache 112 while performing the syncio operation, where a metadata track may need to get updated to store statistics for determining what destage mechanisms to use to destage tracks from the cache 112.

[0032] If at block 406 it is determined that the CPU 138 needs to update a metadata track ("Yes" branch 408), then control proceeds to block 410 in which the CPU 138 indicates (at block 410) in an entry of the reserved buffer the update needed to the metadata track. Control proceeds to block 412, in which the CPU 138 determines whether the reserved buffer is full. If so, ("Yes" branch 414) then the CPU 138 adds (at block 416) the reserved buffer to a list of used buffers in the buffer pool 142, and control returns to block 402. If not ("No" branch 418), control returns to block 404 where the CPU 138 continues to use the existing reserved buffer that is not full.

[0033] If at block 406 it is determined that the CPU 138 does not need to update a metadata track ("No" branch 420), then control returns to block 402.

[0034] Therefore FIG. 4 illustrates how the buffer pool 142 is managed to provide free buffers, and how used buffers are generated and placed in the buffer pool 142.

[0035] FIG. 5 illustrates a flowchart 500 that shows how a background task asynchronously updates metadata tracks, in accordance with certain embodiments. In certain embodiments, the operations shown in FIG. 5 may be performed within the storage controller 102 by one or more background tasks 134 that execute in the storage controller 102.

[0036] Control starts at block 502 in which the background task 134 starts executing operations or continues to execute operations. The background task 134 determines (at block 504) if there is a used buffer in the buffer pool 142. If so, ("Yes" branch 506) then the background task 134 initiates processing (at block 508) of the used buffer from the buffer pool 142. The background task 134 processes entries of the used buffer to update (at block 510) one or more metadata tracks 128, 130. Therefore, asynchronous update of the metadata tracks 128, 130 takes place. Once all entries of the used buffer are processed, the background task 134 indicates (at block 512) that the used buffer is a free buffer and control returns to block 502.

[0037] If at block 504, the background task 134 determines (at block 504) that there is no used buffer in the buffer pool 142 ("No" branch 514) then control returns to block 502.

[0038] Therefore, the operations shown in FIG. 5 show mechanisms to asynchronously update metadata tracks, i.e., the update of metadata tracks is asynchronous with respect to syncio operations.

[0039] FIG. 6 illustrates another flowchart 600 that shows how a background task 134 asynchronously updates metadata tracks 128, 130, in accordance with certain embodiments. In certain embodiments, the operations shown in FIG. 6 may be performed within the storage controller 102 by one or more background tasks that execute in the storage controller 102.

[0040] Control starts at block 602 in which the background task 134 starts executing operations or continues to execute operations. The background task 134 selects (at block 604) a predetermined number (e.g., 10) of used buffers from the buffer pool 142. Control proceeds to block 606, in which the background task 134 generates one or more groups, wherein a group stores all the entries in the selected buffers that store update information of the same metadata track. For each entry in a group, the background task 134 accesses the metadata track whose update information is stored in the entry and updates (at block 608) the metadata track with the update, i.e., each entry of a group is used to update the same metadata track. The one or more groups generated in block 606 are processed in block 608.

[0041] From block 608, control proceeds to block 610, in which once all groups are processed, the used buffers selected by the background task in block 604 are indicated to be free buffers in the buffer pool 142.

[0042] Therefore, FIG. 6 illustrates mechanisms for converting a plurality of used buffers into free buffers in the buffer pool 142.

[0043] FIG. 7 illustrates a flowchart 700 that shows how the number of background tasks is adjusted to maintain an adequate number of free buffers in the buffer pool 142, in accordance with certain embodiments. The operations shown in FIG. 7 may be performed by the background task adjustment process 136 that executes in the storage controller 102.

[0044] Control starts at block 702 in which the background task adjustment process 136 is initiated. From block 702 control proceeds in parallel to blocks 704 and 706.

[0045] At block 702, the background task adjustment process 136 determines if the number of free buffers in the buffer pool 142 is greater than a minimum threshold (e.g., 20). If so, ("Yes" branch 708) control proceeds to block 710 in which the background task adjustment process 136 continues to maintain the current number of background tasks. If not ("No" branch 712), then the background task adjustment process 136 increments (at block 714) the number of background tasks by "N" (e.g., if "N" represents the number 5, then the number of background tasks is increased by 5). Thus more background tasks are used to increase the rate at which used buffers are converted to free buffers, if the number of free buffers reach or fall below a minimum threshold.

[0046] At block 706, the background task adjustment process 136 determines if the number of free buffers in the buffer pool 142 is fewer than a maximum threshold (e.g., 30). If so, ("Yes" branch 716) control proceeds to block 718 in which the background task adjustment process 136 continues to maintain the current number of background tasks. If not, ("No" branch 720) then the background task adjustment process 136 decrements (at block 722) the number of background tasks by "M" (e.g., if "M" represents the number 2, then the number of background tasks is decreased by 2). Thus fewer background tasks are used to decrease the rate at which used buffers are converted to free buffers, if the number of free buffers reach or rise above a maximum threshold.

[0047] Therefore, FIG. 7 illustrates certain embodiments to maintain a suitable number of free buffers between a minimum threshold number and a maximum threshold number, by adjusting the number of background tasks that are used to convert used buffers into free buffers.

[0048] FIG. 8 illustrates a flowchart 800 that shows how asynchronous updates of metadata tracks are made in response to a cache hit generated because of a syncio operation, in accordance with certain embodiments. In certain embodiments, the operations shown in FIG. 8 may be performed by the storage controller 102.

[0049] Control starts at block 802 in which a cache hit is generated, in response to receiving an input/output (I/O) command over a bus interface 116, 118. The I/O command over the bus interface 116, 118 is a syncio command. An update for a metadata track is stored (at block 804) in a buffer associated with a central processing unit (CPU) 138 that processes the I/O command, in response to generating the cache hit.

[0050] From block 804, control proceeds to block 806 in which the metadata track is asynchronously updated (i.e., the syncio operation may have already completed at the time the metadata track is updated) from the buffer with the stored update for the metadata track in the buffer.

[0051] Therefore, FIGs. 1-8 illustrate certain embodiments in which the processing of a syncio command by a CPU generates the need for an update of a metadata track because of a cache hit. However, the syncio command is allowed to complete without waiting for the update to the metadata track. The CPU stores the update to the metadata track in a buffer reserved exclusively for the CPU, prior to completion of the processing of the syncio command. A background task copies the update from the buffer to the metadata track at an opportune time. As a result, syncio operations may complete in a timely manner without waiting for update to metadata tracks.

Cloud computing environment

[0052] Cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

[0053] Referring now to FIG. 9 a cloud computing environment 50 of certain embodiments is depicted. As shown, cloud computing environment 50 comprises one or more cloud computing nodes 10 with which local computing devices used by cloud consumers, such as, for example, personal digital assistant (PDA) or cellular telephone 54A, desktop computer 54B, laptop computer 54C, and/or automobile computer system 54N may communicate. Cloud computing nodes 10 may communicate with one another. They may be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof. This allows cloud computing environment 50 to offer infrastructure, platforms and/or software as services for which a cloud consumer does not need to maintain resources on a local computing device. It is understood that the types of computing devices 54A-N shown in FIG. 9 are intended to be illustrative only and that cloud computing nodes 10 and cloud computing environment 50 can communicate with any type of computerized device over any type of network and/or network addressable connection (e.g., using a web browser).

[0054] Referring now to FIG. 10, a set of functional abstraction layers provided by cloud computing environment 50 (FIG. 9) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 10 are intended to be illustrative only and embodiments of the invention are not limited thereto. [0055] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframes, in one example IBM zSeries systems; RISC (Reduced Instruction Set Computer) architecture based servers, in one example IBM pSeries systems; IBM xSeries systems; IBM BladeCenter systems; storage devices; networks and networking components. Examples of software components include network application server software, in one example IBM WebSphere application server software; and database software, in one example IBM DB2 database software (IBM, zSeries, pSeries, xSeries, BladeCenter, WebSphere, and DB2 are trademarks of International Business Machines Corporation registered in many jurisdictions worldwide).

[0056] Virtualization layer 62 provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers; virtual storage; virtual networks, including virtual private networks; virtual applications and operating systems; and virtual clients.

[0057] In one example, management layer 64 may provide the functions described below. Resource provisioning provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources may comprise application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal provides access to the cloud computing environment for consumers and system administrators. Service level management provides cloud computing resource allocation and management such that required service levels are met. Service Level

Agreement (SLA) planning and fulfillment provide pre-arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.

[0058] Workloads layer 66 provides examples of functionality for which the cloud computing environment may be utilized. Examples of workloads and functions which may be provided from this layer include: mapping and navigation; software development and lifecycle management; virtual classroom education delivery; data analytics processing; transaction processing; and asynchronous writing of metadata track in syncio 68 as shown in FIGs 1-9.

Additional Embodiment Details

[0059] The described operations may be implemented as a method, apparatus or computer program product using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. Accordingly, aspects of the embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," "module" or "system." Furthermore, aspects of the embodiments may take the form of a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present embodiments.

[0060] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating

electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0061] Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

[0062] Computer readable program instructions for carrying out operations of the present embodiments may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present embodiments.

[0063] Aspects of the present embodiments are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

[0064] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

[0065] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

[0066] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instruction.

[0067] FIG. 11 illustrates a block diagram that shows certain elements that may be included in the storage controller 102, the hosts 104,106, or other computational devices in accordance with certain embodiments. The system 1100 may include a circuitry 1102 that may in certain embodiments include at least a processor 1104. The system 1100 may also include a memory 1106 (e.g., a volatile memory device), and storage 1108. The storage 1108 may include a non-volatile memory device (e.g., EEPROM, ROM, PROM, flash, firmware, programmable logic, etc.), magnetic disk drive, optical disk drive, tape drive, etc. The storage 1108 may comprise an internal storage device, an attached storage device and/or a network accessible storage device. The system 1100 may include a program logic 1110 including code 1112 that may be loaded into the memory 1106 and executed by the processor 1104 or circuitry 1102. In certain embodiments, the program logic 1110 including code 1112 may be stored in the storage 1108. In certain other embodiments, the program logic 1110 may be implemented in the circuitry 1102. One or more of the components in the system 1100 may communicate via a bus or via other coupling or connection 1114. Therefore, while FIG. 11 shows the program logic 1110 separately from the other elements, the program logic 1110 may be implemented in the memory 1106 and/or the circuitry 1102.

[0068] Certain embodiments may be directed to a method for deploying computing instruction by a person or automated processing integrating computer-readable code into a computing system, wherein the code in combination with the computing system is enabled to perform the operations of the described embodiments.

[0069] The terms "an embodiment", "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "one embodiment" mean "one or more (but not all) embodiments of the present invention(s)" unless expressly specified otherwise.

[0070] The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless expressly specified otherwise.

[0071] The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

[0072] The terms "a", "an" and "the" mean "one or more", unless expressly specified otherwise.

[0073] Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0074] A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention.

[0075] Further, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously.

[0076] When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the present invention need not include the device itself.

[0077] At least certain operations that may have been illustrated in the figures show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified or removed. Moreover, steps may be added to the above described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units.

[0078] The foregoing description of various embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.