BACKGROUND OF THE INVENTION BiCMOS current switching circuits are known, in which a signal applied to a CMOS transistor determines a current through a bipolar transistor. For example, current steering digital-to-analog converters may include a plurality of bipolar devices, each bipolar device having a respective CMOS device associated with it, and with the total current drawn by the bipolar devices being determined by the inputs to the CMOS devices.

As an example of this, US-5,548,288 describes a current cell and current switch for use in a current- steering digital-to-analog converter. In the circuit described therein, an output current is determined by the digital signal applied to the circuit inputs.

However, the circuit described therein has the disadvantage that it includes a relatively large number of components and hence that it uses a relatively large area in an integrated circuit.

SUMMARY OF THE INVENTION The present invention provides a circuit which, in some embodiments, can be implemented using fewer components than at least some of the prior art circuits, and hence uses a smaller area in an integrated circuit.

More specifically, one embodiment of a first aspect of the invention provides a BiCMOS circuit which includes a first bipolar transistor which, in operation, draws a current. The collector of the first

bipolar transistor is connected to a voltage source through a CMOS transistor, and to a circuit output through a second bipolar transistor. The output current drawn through the second bipolar transistor depends on whether the CMOS transistor is turned on or off by a control voltage applied thereto.

According to a second aspect of the invention, there is provided a digital-to-analog converter which <BR> <BR> <BR> <BR> includes a plurality of BiCMOS circuits in accordance with the first aspect of the invention. The respective first bipolar transistors thereof preferably form respective current mirror circuits with a further bipolar transistor, and draw respective currents which can be added to form a total output current which depends on the respective control voltages applied to the respective CMOS transistors.

According to a third aspect of the invention, there is provided a charge pump circuit which includes <BR> <BR> <BR> <BR> two BiCMOS circuits in accordance with the first aspect of the invention. A first circuit is configured as a current source, and a second is configured as a current sink. Controlling the inputs to the two circuits results in changes in the output current.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a first current sink circuit in accordance with the invention.

Figure 2 is a circuit diagram of a second current sink circuit in accordance with the invention.

Figure 3 is a circuit diagram of a third current sink circuit in accordance with the invention.

Figure 4 is a circuit diagram of a charge pump circuit in accordance with the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Figure 1 shows a first circuit in accordance with the invention, acting as a switched current sink. The circuit of Figure 1 is based around a conventional

bipolar emitter follower augmented current mirror circuit 2, including a constant current source 4, producing a constant current Iref, connected between an appropriate bipolar positive voltage supply Vcc and the collector of an NPN bipolar transistor 6, the emitter of which is connected to ground through a resistor 8 of resistance R. The base of the transistor 6 is connected to the base of a further NPN bipolar transistor 10, the emitter of which is connected to ground through a resistor 12. In this illustrated embodiment, the resistor 12 has a resistance value R, equal to that of the resistor 8. The effect of the resistors 8,12 is to control the currents through the transistors 6,10. It will be appreciated that these resistors can be omitted from the circuit, and any necessary scaling can then be achieved by scaling the emitter areas of the transistors.

The current mirror circuit 2 further includes a third NPN bipolar transistor 14, the base of which is connected to the collector of the transistor 6, the collector of which is connected to the positive voltage supply Vcc, and the emitter of which is connected to the bases of the transistors 6,10. It will be appreciated that this emitter follower transistor 14 may be omitted, if the resulting decrease in the accuracy of the current mirror is acceptable.- As part of the switch in accordance with this illustrated embodiment of the invention, a fourth NPN bipolar transistor 16 has its emitter connected to the collector of the transistor 10, and its collector connected to an output terminal 18. The base of the transistor 16 is biased to a voltage level set by a voltage source 20, the negative terminal of which is connected to ground. For example, this voltage level may be set to 3. Vbe, where Vbe is the base-emitter voltage required to turn the transistor on.

Finally, the circuit of Figure 1 includes a PMOS transistor 22, the source of which is connected to an appropriate positive MOS voltage supply Vdd, and the drain of which is connected to the connection of the emitter of the transistor 16 and the collector of the transistor 10. The gate terminal of the PMOS transistor 22 is connected to a control input 24, which receives a logic input signal.

When the input signal at the control input 24 is high, the MOS transistor-22 is turned off, and the current mirror circuit 2 operates in a conventional way. Thus the bipolar-transistor 16 is turned on, and the collector current of transistor 10 is drawn through the transistor 16, and hence appears as the output current drawn through the output terminal 18. If, as in this illustrated embodiment, the resistance value of the resistor 12 is equal to that of the resistor 8, the output current can be made equal to Iref, the current generated by the current source 4.

If, on the other hand, the input signal at the control input 24 is low-, the MOS-transistor 22 is turned on. In that case, the voltage at the connection of the emitter of the transistor 16 and the collector of the transistor 10 is high (close-to Vdd, depending on the characteristics of the MOS transistor 22), and the transistor 16 is turned off. Hence, all of the collector current of the transistor 10 is drawn through the MOS transistor 22.

Thus, the output current, drawn through the output terminal 18, is zero.

The output current can be used to power up or down any subsequent circuit block. It can thus be seen that the output current can be switched by the digital signal applied to the gate of the MOS transistor 22, without requiring switching of the control signal level between CMOS and CML levels. Moreover, if a subsequent

controlled circuit block is a high voltage block, this can be controlled by a low voltage CMOS signal.

Figure 2 shows a digital-to-analog converter, based on the switch of Figure 1. In the D-A converter of Figure 2, there are multiple inputs, for-example receiving different bits of an input digital signal, and respective outputs. Each such input and output are associated with a respective current mirror circuit of the type shown in Figure 1.

In Figure 2, constant current source 104, producing a constant current Iref, is connected between an appropriate bipolar positive voltage supply Vcc and the collector of an NPN bipolar transistor 106, the emitter of which is connected to ground through a resistor 108 of resistance R. The transistor 106 is common to, and forms one half of, each of the respective current mirror circuits associated with the different inputs.

As in Figure 1, the circuit further includes a bipolar transistor 114, the base of which is connected to the collector of the transistor 106, the collector of which is connected to the positive voltage supply Vcc, and the emitter of which is connected to the base of the transistor 106.

Also as in Figure 1, the circuit of Figure 2 includes a further NPN bipolar transistor 110, the base of which is connected to the base of the transistor 106, and the emitter of which is connected to ground through a resistor 112.

In this illustrated embodiment, the resistor 112 has a resistance value R, equal to that of the resistor 108, and so the current drawn through the transistor 110 is equal to Iref, the current produced by the current source 104.

A fourth NPN bipolar transistor 116 has its emitter connected to the collector of the transistor

110, and its collector connected to an output terminal OP1. The base of the transistor 116 is biased to a voltage level set by a voltage source 120, the negative terminal of which is connected to ground. For example, this voltage level may be set to 3. Vbe, where Vbe is the base-emitter voltage required to turn the transistor on.

Finally, the first current mirror circuit includes a PMOS transistor 122, the source of which is connected to an appropriate positive MOS voltage supply Vdd, and the drain of which is connected to the connection of the emitter of the transistor 116 and the collector of the transistor 110. The gate terminal of the PMOS transistor 122 is connected to a control input IP1, which receives a logic input signal.

Similarly, the second current mirror circuit includes a further NPN bipolar transistor 130, the base of which is connected to the base of the transistor 106, and the emitter of which is connected to ground through a resistor 132.

In this illustrated embodiment, the resistor 132 has a resistance value R/n, that is, an integer fraction of that of the resistor 108.

A further NPN bipolar transistor 136 has its emitter connected to the collector of the transistor 130, and its collector connected to an output terminal OP2. Like the transistor 116, the base of the transistor 136 is biased to the voltage level set by the voltage source 120.

Finally, the second current mirror circuit includes a PMOS transistor 142, the source of which is connected to the positive MOS voltage supply Vdd, and the drain of which is connected to the connection of the emitter of the transistor 136 and the collector of the transistor 130. The gate terminal of the PMOS transistor 142 is connected to a control input IP2,

which receives a logic input signal.

It will be appreciated that, although the circuit shown in Figure 2 has two circuit inputs, two outputs, and two current mirror circuits, it may include any convenient number of such circuits, with bipolar transistors 130,136, resistor 132 and PMOS transistor 142 being repeated as required, and perhaps with different resistance values of the resistor (s).

The circuit of Figure 2 operates in a similar way to that of Figure 1. Thus when the input signal at one of the control inputs IP1 or IP2 is high, the associated MOS transistor 122 or 142 is turned off, and the collector current of the transistor 110 or 130 is drawn through the transistor 116 or 136, and hence appears as the output current drawn through the output terminal OP1 or OP2.

If, on the other hand, the input signal at one of the control inputs OP1, OP2 is low, the associated MOS transistor 122,142 is turned on. In that case, the transistor 116 or 136 is turned off. Hence, all of the collector current-of the transistor 110 or 130 is drawn through the MOS transistor 122 or 142, and the output current, drawn through the output terminal OP1 or OP2 is zero.

The output currents at the output terminals OP1 and OP2 may be summed to give an overall analog output current in response to the digital input at the input terminals IP1 and IP2.

If, as in this illustrated embodiment, the resistance value of the resistor 112 is equal to R, namely that of the resistor 108, the output current at output terminal OP1 can be made equal to Iref, the current generated by the current source 104.

Meanwhile, if the resistance value of the resistor 132 is equal to R/n, namely an integer fraction of that of the resistor 108, the output current at output terminal

OP2 can be made equal to n. Iref, an integer multiple of the current generated by the current source 104.

Thus, in this example, by selection of the digital signal applied to the two inputs IP1, IP2, the overall output current can be made equal to 0, Iref, n. Iref, or (n+l). Iref. For example, this may be particularly useful if n=2. Where there are more than two inputs and outputs, the resistance values of the resistors may be chosen as values of R/n, with n being successive powers of 2 in the different current mirror circuits.

Figure 3 shows an alternative circuit in accordance with the invention, in which components which correspond to components of the circuit of Figure 1 are indicated by the same reference numerals. In the circuit of Figure 3, there is no current mirror, but the current through the transistor 10 arises because there is a reference voltage source 160 connected between the base of the transistor 10 and the ground rail. The voltage drop across the resistor 12 is set by the reference voltage and the base-emitter voltage of the transistor 10, and the value of the resistor 12 then determines the current through the transistor 10.

The circuits have been described herein as current sinks, but analogous current source versions may be made by using PNP bipolar transistors and NMOS transistors instead of PMOS at the control inputs.

Figure 4 shows a charge pump circuit in accordance with the invention, made up of two of the circuits described previously, namely a current sink circuit 180, and a current source circuit 182.

The current sink circuit 180 includes an NPN bipolar transistor 184, the collector terminal of which is connected to a constant current source 186, producing a constant current Iref. The emitter terminal of the transistor 184 is connected to ground through a resister 188. The base terminal of the

transistor 184 is connected to the base terminal of a further NPN bipolar transistor 190, the emitter terminal of which is connected to ground through a further resister 192. A third NPN bipolar transistor 194 has its base terminal connected to the collector terminal of the transistor 184, its collector terminal connected to a positive supply voltage Vcc, and its emitter terminal connected to the base terminals of the transistors 184,190. A fourth NPN bipolar transistor 196 has its emitter terminal connected to the collector terminal of the transistor 190, and its collector terminal connected to an output point at which an output value IOUT is obtained. The base terminal of the transistor 196 is biased to an appropriate level by a voltage source 198.

Finally, the current sink circuit 180 includes a PMOS transistor 200, the source of which is connected to a positive voltage supply Vdd, and the drain of which is connected to the node between the emitter of the transistor 196 and the collector of the transistor 190. The gate terminal of the PMOS transister 200 is connected to a control input IP2, which receives a logic input signal.

As described previously with reference to the circuit of Figure 1, when the input signal at the terminal IP2 is high, a current equal to the reference current Iref is drawn from the output terminal IOUT, whereas, when the input signal is low, no current is drawn.

As previously described, the current source circuit 182 is analogous to the current sink circuit 180.

More specifically, the current source circuit 182 includes a PNP transistor 202, the emitter terminal of which is connected through a resistor 204 to a positive supply voltage Vcc. The collector terminal of the

transistor 202 is connected to the current source 186, and the base terminal thereof is connected to the base terminal of a second PNP bipolar transistor 206. The emitter terminal of this second PNP transistor is also connected to the positive supply rail through a respective resistor 208, and the collector terminal is connected to the emitter terminal of a third PNP transistor 210. The collector terminal of this third transistor 210 is connected to the output terminal IOUT, and the base terminal thereof is biased to an appropriate voltage level by a voltage supply 212.

Meanwhile, a fourth PNP bipolar transistor 214 has its emitter terminal connected to the base terminals of the transistors 202,206, its base terminal connected to the collector terminal of the transistor 202, and its collector terminal connected to ground.

An NMOS transistor 216 has its source terminal connected to ground, its drain terminal connected to the node between the collector terminal of the transistor 206 and the emitter terminal of the transistor 210, and has its gate terminal connected to an input terminal IP1. When the signal at this input is low, a current equal to the reference current Iref is supplied to the output terminal IOUT, whereas, when the input signal supplied to the input terminal IP1 is high, no current is supplied.

Thus, the overall circuit acts as a charge pump circuit, with the output current depending on the values of the input signals which are applied.

When both inputs are low, a current equal to the reference current Iref is supplied to the output terminal IOUT. When both inputs are high, a current equal to the reference Iref is drawn from the output terminal IOUT. When the input signal at the terminal IP1 is high, and the input signal at the terminal IP2 is low, no current is supplied to the output. When the

signal at the input terminal IP1 is low, and the signal at the input terminal IP2 is high, the current sink and current source circuits are both active, and the current supplied to the output terminal is nominally zero. However, in this condition, any mismatch between the two circuits will result in a leakage current, and so, for practical purposes, this state is preferably avoided.

There is thus described a circuit which allows a low voltage CMOS signal to control a bipolar current source or sink circuit, without requiring large numbers of components or large surface areas in an integrated circuit.