BUS ARBITRATION DEVICE - PANASONIC CORP

Title:

BUS ARBITRATION DEVICE

Document Type and Number:

WIPO Patent Application WO/2011/089660

Kind Code:

A1

Abstract:

Disclosed is a bus arbitration device capable of transferring requests from specified masters to slaves at low latency, and of securing bandwidth required by other masters. An arbitration circuit (108) receives read/write requests at given intervals from a CPU or other master (101), for which low latency is required. The master (101) thereby carries out low latency memory access. Bandwidth necessary for broadband is secured by allocating excess bandwidth not used by the master (101) to DMA controllers or other masters (102, 103), for which broadband is required. The arbitration circuit (108) constrains the reception of low-priority read/write requests from the masters (102, 103) when read/write requests are being stalled upon a buffer (119) within a slave (118).

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Inventors:

MAEDA TAKASHI
SUMIDA MAMORU
HASHIMOTO KOUKICHI
MATSUSHITA MASATOSHI

Application Number:

PCT/JP2010/003536

Publication Date:

July 28, 2011

Filing Date:

May 26, 2010

Export Citation:

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Assignee:

PANASONIC CORP (JP)
MAEDA TAKASHI
SUMIDA MAMORU
HASHIMOTO KOUKICHI
MATSUSHITA MASATOSHI

International Classes:

G06F13/372; G06F13/36; G06F13/362

Foreign References:

JP2003186823A	2003-07-04
JP2008097462A	2008-04-24
JP2007207024A	2007-08-16
JP2004246862A	2004-09-02

Attorney, Agent or Firm:

OGURI, Shohei et al. (JP)
Shohei Oguri (JP)

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