Title:
CACHE MEMORY AND CONTROL METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2018/179044
Kind Code:
A1
Abstract:
In a cache memory (2), a main unit (20) stores a copy of part of the data stored in a memory space to be accessed, and also stores memory address information associated with that part of the data, on a per cache line basis. The memory space is divided into a plurality of memory regions. An address generation unit (10) generates a cache memory address (CMA) from a memory address (MA) specified by an external access request, on the basis of a memory region among the plurality of memory regions that corresponds to the memory address (MA) specified by the access request. The main unit (20) is then searched on the basis of this cache memory address (CMA). In this way, the memory regions are associated with different ranges of cache lines, which are searched or replaced as units.
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Inventors:
YAMAGUCHI KEITA (JP)
Application Number:
PCT/JP2017/012355
Publication Date:
October 04, 2018
Filing Date:
March 27, 2017
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
G06F12/12
Domestic Patent References:
| WO2010089799A1 | 2010-08-12 |
Foreign References:
| JPH04209049A | 1992-07-30 | |||
| JP2001282617A | 2001-10-12 |
Attorney, Agent or Firm:
FUKAMI PATENT OFFICE, P.C. (JP)
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