Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
CAPACITIVE-COUPLED NON-VOLATILE THIN-FILM TRANSISTOR STRINGS IN THREE DIMENSIONAL ARRAYS
Document Type and Number:
WIPO Patent Application WO/2018/039654
Kind Code:
A4
Abstract:
Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

Inventors:
HARARI, Eli (20238 Hill Avenue, Saratoga, California, 95070, US)
Application Number:
US2017/048768
Publication Date:
April 19, 2018
Filing Date:
August 25, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SUNRISE MEMORY CORPORATION (140 W. Main Street, 2nd FloorLos Gatos, California, 95030, US)
International Classes:
H01L21/02; H01L21/28; H01L21/3213; H01L21/768; H01L23/528; H01L29/06; H01L29/08; H01L29/10; H01L29/423; H01L29/51; H01L29/66
Attorney, Agent or Firm:
KWOK, Edward C. (VLP LAW GROUP LLP, Suite 820555 Bryant Stree, Palo Alto California, 94301, US)
Download PDF:
Claims:
AMENDED CLAIMS

received by the International Bureau on 26 FEB 2018 (26.02.2018)

CLAIM

What is claimed is:

1. A memory structure, comprising: a semiconductor substrate having a substantially planar surface, wherein the semiconductor substrate has circuitry formed therein; a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a second direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers each comprise polysilicon or silicon germanium; a charge-trapping material; and a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the charge-trapping material, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of thin film transistors, including two or more thin-film storage transistors, that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent charge-trapping material and the conductors within the group, wherein (a) the first, second and third semiconductor layers in each active strip provide, respectively, channel,

89 source and drain regions of the thin-film transistors, (b) the thin-film transistors of each active strip sharing source and drain regions in common, and (c) one of the shared source and shared drain regions is electrically isolated relative to the circuitry, except when one or more of a selected group of thin-film transistors formed in the active strip are rendered conducting to charge a parasitic or intrinsic capacitor of the electrically isolated shared region by a current through the other shared region to a predetermined voltage.

2. The memory structure of claim 1, further comprising a second plurality of conductors formed along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin- film storage transistors.

3. The memory structure of claim 2, wherein the second plurality of conductors are formed between the planar surface and the active strips, the memory structure further comprising a third plurality of conductors formed above the active strips along the first direction, the third plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film storage transistors.

4. The memory structure of claim 3, wherein the selected ones of the first plurality of conductors that are connected to the second plurality of conductors and the selected ones of the first plurality of conductors that are connected to the third plurality of conductors are provided on opposite sides of an active strip.

5. The memory structure of claim 1 , wherein each active strip further comprises at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one or both of the second semiconductor layer and the third semiconductor layer.

6. The memory structure of claim 1 wherein, during a read or program operation, only the conductor associated with an addressed storage transistor of a NOR string is momentarily raised to the predetermined voltage required for the read or program operation,

90 while conductors associated with all other storage transistors of the NOR string held at a voltage below a threshold voltage of an erased storage transistor.

7. The memory structure of claim 6, wherein storage transistors associated with active strips on more than one plane are programmed in a single concurrent programming operation.

8. The memory structure of claim 6 wherein the second or third semiconductor layer of each active strip in one or more planes is appropriately concurrently pre-charged to a predetermined voltage associated with a read operation, prior to carrying out one or more read operations of addressed storage transistors in one or more of the planes while the second or third semiconductor layer holds substantially the predetermined voltage by virtue of capacitance along its associated active strip.

9. The memory structure of claim 1, wherein data stored in one or more of the storage transistors have a data retention time shorter than a year and a program/erase cycle endurance greater than 10,000 program/erase cycles.

10. The memory structure of claim 9, wherein electric charge in each storage transistor sets the storage transistor to a threshold voltage corresponding to one of two or more charge states.

11. The memory structure of claim 1 , further comprising a dopant diffusion-blocking layers between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.

12. The memory structure of claim 1, wherein the channel region of each thin-film storage transistor is connected to the semiconductor substrate by a pillar of semiconductor material of the first conductivity type, wherein the semiconductor substrate provides the channel region of each thin-film storage transistor through the pillar a predetermined back bias voltage that suppresses sub-threshold leakage during a read operation or an erase voltage during an erase operation.

91

13. The memory structure of claim 1, wherein the length of the channel region is sufficiently short to effectuate erase through lateral hopping conduction and tunneling out of stored charge under fringing electric fields between the first, second and third semiconductor layers and corresponding ones of the first plurality of conductors.

14. The memory structure of claim 1, wherein the thin-film transistors of the semiconductor structure are organized into addressable memory pages each belonging to a corresponding storage plane of adjacent NOR strings, wherein each memory page comprises a group of thin-film storage transistors from the corresponding storage plane that are accessed simultaneously by activating one of the second plurality of conductors, one of the third plurality of conductors or one conductor in each of the second and third plurality of conductors.

15. The memory structure of claim 14, wherein the thin-film storage transistors are organized into addressable memory slices, each memory slice comprising adjacent memory pages each of a different storage plane in a stack.

16. The memory structure of claim 15, wherein the thin-film storage transistors are organized into addressable memory quadrants, each quadrant comprising a plurality of adjacent memory slices.

17. The memory structure of claim 16, wherein the thin-film storage transistors are organized into memory blocks, each memory block comprising a two-by-two configuration of adjacent memory quadrants.

18. The memory structure of claim 17, wherein thin-film storage transistors in a first one of the quadrants and a second one of the quadrants share a common set of circuitry at the surface of the semiconductor substrate.

19. The memory structure of claim 1, wherein each NOR string is individually addressable, and wherein a storage thin- film transistor in each of a plurality of the NOR strings are programmed, erased, and read simultaneously.

92

20. The memory structure of claim 1, wherein the circuitry at the surface of the semiconductor substrate charges the intrinsic capacitor selectively to one of: a read voltage, a program voltage, a program-inhibit voltage, an erase voltage, or voltages for setting the programmable thin film transistors of NOR strings designated as reference strings.

21. The memory structure of claim 20 wherein, during a read operation of a selected thin-film storage transistor in each of a selected plurality of NOR strings, (i) the selected group of thin-film storage transistors in each of the selected NOR strings charge the intrinsic capacitor of the floating one of the second and third semiconductor layers of the NOR string to a predetermined voltage from the circuitry at the surface of the semiconductor substrate; (ii) thereafter, the other one of the second and third semiconductor layers of each selected NOR string is charged to a read- sense voltage and is connected to a sense amplifier in the circuitry at the surface of the semiconductor substrate; and (iii) corresponding ones of the first plurality of conductors associated with the selected thin-film storage transistors are set to a sequence of predetermined read voltages or a voltage ramp while all unselected conductors of the first plurality of conductors are held in their non-conducting state.

22. The memory structure of claim 1 wherein, during a programming operation, intrinsic capacitors of the source region, the drain region and the channel region of a selected thin-film storage transistor are each momentarily pre-charged to a virtual ground voltage or to a program-inhibit voltage.

23. The memory structure of claim 14, wherein one or more spare NOR strings are provided in each storage plane for replacing any one of a plurality of NOR strings in the same storage plane.

24. The memory structure of claim 14, wherein one or more of the storage planes are designated redundant planes, the redundant planes providing spare NOR strings for replacing NOR strings in the other storage planes, or for replacing memory pages on the other storage planes.

93

25. The memory structure of claim 14, wherein the charged intrinsic capacitors are refreshed in the background in a standby mode or charging is initiated for selected memory blocks in anticipation of impending read operations, so as to allow a fast subsequent concurrent read or a fast subsequent random accessed read of thin-film storage transistors in one or more memory pages on one or more storage planes.

26. The memory structure of claim 1, wherein the circuitry at the surface of the semiconductor substrate comprises a data integrity circuit which, upon detecting an error, communicates the error to an on-chip error correcting circuitry or to an external system controller, thereby enabling the on-chip circuitry or the external system controller to carry out a data recovery and program-refresh operation.

27. The memory structure of claim 1, wherein each active strip comprises a first NOR string formed along one side of the active strip and a second NOR string formed along the other side of the active strip, wherein the conductors between the first NOR string of a first active strip and the second NOR string of an adjacent active strip serve as shared gate electrodes between corresponding thin-film storage transistors of the first NOR string and the second NOR string, thereby forming related transistor pairs, wherein the thin-film storage transistors of the first NOR string serve as reference transistors for corresponding thin-film storage transistors in the second NOR string, wherein each reference transistor holds a programmed state when the other of the related transistor pair holds an erased state, and vice versa, and wherein output signals from the thin-film storage transistors of a related transistor pair are fed simultaneously into a differential sense amplifier to determine the data represented by the output signals.

28. The memory structure of claim 15, wherein thin-film storage transistors in one or more memory pages or memory slices within a predetermined distance from the circuitry at the surface of the semiconductor substrate are configured to operate as related transistor pairs ("high speed configuration").

29. The memory structure of claim 28, wherein the remainder of the pages or slices are configured to operate with one reference transistor for two or more thin-film storage transistors

94 ("low-cost configuration") within the memory pages or slices.

30. The memory structure of claim 29 wherein, under the low-cost configuration, more than one binary bit of information is stored in each thin-film storage transistor and wherein more than one reference NOR string is provided to read the stored multibit information.

31. The memory structure of claim 29, wherein the thin-film storage transistors operating under the high-speed configuration store on-chip resource management data for use by an external controller, wherein the on-chip resource management data includes one or more of: an updatable file allocation table for files stored in the memory circuit, a unique identifier index number, a program/erase cycle count, chip temperature, and a time- stamp that is appended to each stored data file when it is updated.

32. The memory structure of claim 14, wherein the circuitry at the surface of the substrate further comprises a pipeline streaming circuitry that overlaps sensing a memory page of stored data in sense amplifiers and transferring the sensed data to a data buffer for serial bit stream, or parallel word- wide output from the memory circuit, with concurrently reading a next memory page of the stored data from the memory structure for sensing in the sense amplifiers.

33. The memory structure of claim 1, wherein the first semiconductor layer is provided in cavities or recesses that result from removal of all or part of a sacrificial layer.

34. The memory structure of claim 33, wherein the first semiconductor sublayer has a thickness that is sufficiently thin to be readily depleted when an appropriate voltage is applied between the conductors and the second and third semiconductor sublayers.

35. The memory structure of claim 33, wherein adjacent NOR strings formed on opposite sides of an active strip have their respective channels isolated from each other by a narrow spine.

36. In an integrated circuit, a memory structure on a semiconductor substrate comprising isolated NOR strings of non- volatile or quasi-volatile thin-film transistors arranged in a plurality of stacks, the stacks being spaced apart along a first direction, wherein each NOR string is individually accessed from circuitry in the semiconductor substrate to temporarily charge the NOR string's intrinsic capacitance to a predetermined voltage selected from voltages used for programming, programming-inhibiting, erasing or reading of individual thin-film transistors in the NOR string, and wherein the thin-film transistors in each NOR string share a source sublayer and a drain sublayer, each thin- film transistor further comprising a channel sublayer, a word line conductor and charge trapping material in between a word line conductor and a channel sublayer.

37. The memory structure of claim 36, wherein the NOR strings are arranged one on top of the other in each stack, each NOR string extending along a second direction that is substantially parallel to the semiconductor substrate with spaced apart word line conductors extending along a third direction that is substantially perpendicular to the semiconductor substrate, and wherein currents in the thin-film transistor flow along a direction substantially parallel to the third direction.

38. The memory structure of claim 36, wherein the NOR strings are provided spaced apart word line conductors one on top of another each extending along a second direction that is substantially parallel to the semiconductor substrate, each NOR string extending along a third direction that is substantially perpendicular to the semiconductor substrate, and wherein currents in the thin-film transistor flow along a direction substantially parallel to the second direction.

39. The memory structure of claim 36, wherein selected ones of the NOR strings are addressed and charged individually and programmed, program-inhibited, erased or read together in groups of one or more NOR strings.

40. The memory structure of claim 36, wherein a sacrificial sublayer is provided between the shared source and drain sublayers of each NOR string prior to formation of the channel sublayer.

41. The memory structure of claim 40, wherein the sacrificial sublayer is selectively etched in part or in whole to form cavities between the second and third sublayers,

42. The memory structure of claim 41 , wherein the channel sublayers of all thin-film transistors in the NOR strings of each stack are formed simultaneously.

43. The memory structure of claim 40, wherein the channel sublayers for the thin- film transistors in each stack are formed simultaneously after the charge-trapping material is provided.

44. A memory circuit, comprising: a semiconductor substrate having a substantially planar surface and including circuitry formed therein and thereon; a dielectric layer formed over the planar surface of the semiconductor substrate; a semiconductor structure formed over the dielectric layer, comprising a first semiconductor sublayer of a first conductivity type provided between second and third semiconductor sublayers each of a second conductivity type, the first, the second and third semiconductor sublayers providing the semiconductor structure a sidewall; a conductor substantially outside the semiconductor structure substantially aligned with a portion of the first semiconductor sublayer; and a charge- storage layer provided over the sidewall of the semiconductor structure between the conductor and the aligned portion of the semiconductor sublayer, wherein the first, second and third semiconductor sublayers providing, respectively, channel, source and drain regions of a thin-film storage transistor, wherein the conductor provides a gate electrode to the thin-film storage transistor, and wherein one of the second and third semiconductor sublayers is electrically isolated relative to the circuitry formed in the semiconductor substrate, except when the channel region is rendered conducting.

45. The memory circuit of claim 44, wherein a separation between the second and

97 third semiconductor sublayers has a thickness substantially defined by a sacrificial material, and wherein the first semiconductor sublayer is provided after at least a portion of the sacrificial material is removed from between the second and third semiconductor sublayers.

46. The memory circuit of claim 45, wherein a portion of the sacrificial material remains between the second and third semiconductor sublayers to provide mechanical support and isolation.

47. The memory circuit of claim 44, further comprising a dopant diffusion-blocking layer between the first semiconductor sublayer and one or both of the second and the third semiconductor sublayer.

48. A semiconductor manufacturing process, comprising: providing a semiconductor substrate and forming circuitry therein and thereon; providing a plurality of active layers and buried contacts over the semiconductor substrate, each active layer comprising a first semiconductor layer of a first conductivity between second and third semiconductor layers of a second conductivity, wherein each active layer is electrically isolated from a lower active layer or the semiconductor substrate by a dielectric layer, except at the buried contacts, wherein the buried contacts connect one or more of the second or third semiconductor layers of each active layer to the circuitry of the semiconductor substrate; patterning and etching the plurality of active layers anisotropically to provide a first set of trenches separated from each other along a first direction, the trenches having sidewalls running lengthwise in a second direction, the first and second directions being substantially parallel to a surface of the semiconductor substrate; providing a charge-trapping material conformally over the sidewalls of the trenches; filling the trenches with a conductive material;

98 patterning and etching a portion of the conductive material, such that the remaining conductive material forms a plurality of conductors that extends lengthwise along a third direction that is substantially perpendicular to the surface of the

semiconductor substrate; providing a layer of dielectric material over the active layers except at a plurality of contact openings that expose the conductors; and providing conductive wiring that connects the exposed conductors at the contact openings to the circuitry in the semiconductor substrate.

49. The process of Claim 48, further comprising providing a second set of conductive wiring that includes contacts for connecting to the conductors, wherein the steps of patterning and etching the trenches expose the contacts such that electrical connection to the conductors is achieved when the conductors are formed.

50. The process of Claim 48, wherein the charge-trapping material is provided to have a thickness such that electrons from the first, second and third semiconductor layers tunnel into the charge-trapping material through a Fowler- Nordheim tunneling or direct tunneling mechanism when a voltage exceeding a predetermined value is applied between one of the conductors and the first, second and third semiconductor layers.

51. The process of Claim 48, wherein the charge-trapping material is provided to have a thickness such that electrons from one of the second and third semiconductor layers are injected into the charge-trapping material over the channel through a channel hot-electron injection mechanism.

52. A semiconductor manufacturing process for three-dimensional memory blocks, comprising: providing a semiconductor substrate and forming circuitry therein and thereon; forming a first set of low resistivity conductor wirings above the semiconductor

99 substrate and connected to the circuitry through via openings; depositing and planarizing a first isolation layer; forming a first set of buried contacts in the first isolation layer to provide electrical connections to the circuitry in the semiconductor substrate; forming over the first isolation layer a first plane of semiconductor material, the first plane of semiconductor material comprising a layer of a first sacrificial material defining a space for a first semiconductor sublayer to be formed, and second and third semiconductor sublayers of a first conductivity type separated by the layer of the first sacrificial material, wherein the first set of buried contacts provide electrical contact between the second or the third semiconductor sublayer and the circuitry in the semiconductor substrate; patterning and removing portions of the first plane of semiconductor material to make room for a next set of the buried contacts; repeating for a predetermined number of times the steps of (i) deposition and planarizing an additional isolation layer; (ii) forming the next set of buried contacts to provide electrical connections to the circuitry in the semiconductor substrate; (iii) forming over the additional isolation layer and the next set buried contacts to provide an additional plane of semiconductor material, the additional plane of semiconductor material comprising a layer of the first sacrificial layer, and second and third

semiconductor sublayers of the first conductivity type separated by the layer of the first sacrificial material, wherein the additional second semiconductor layer or the third semiconductor sublayer of the additional plane of semiconductor are electrically contacted by one of the additional set of buried contacts; and (iv) patterning and removing portions of the additional plane of semiconductor material to provide room for an additional next set of buried contacts; and patterning and anisotropically etching the isolation layers and the planes of

100 semiconductor material to form an array of active strips.

53. The process of claim 52, further comprising simultaneously annealing the first plane and each of the additional planes of semiconductor material to activate dopants in the second and third semiconductor sublayers.

54. The process of claim 52, wherein each plane of the semiconductor material is annealed individually using shallow annealing by excimer laser.

55. The process of claim 52, wherein the patterning and anisotropically etching of the first isolation layer, the first plane of semiconductor material, the additional isolation layers and the additional planes of semiconductor materials are performed using a hard mask.

56. The process of claim 52, wherein the array of active strips comprises a plurality of stacks of active strips, each stack being separated along a first direction from an adjacent stack by one of a first set of trenches, each stack having sidewalls running lengthwise in a second direction, the first and second directions being substantially parallel to a surface of the semiconductor substrate.

57. The process of claim 56, further comprising filling the trenches between the stacks of active strips using a second sacrificial material.

58. The process of claim 57, further comprising: forming a second set of trenches by partially etching the second sacrificial material to expose portions of one or both sidewalls of the stacks of active strips and the bottom of each stack of active strips; and removing at least a portion of the first sacrificial material from all active strips, wherein the removing is performed using an etchant that selectively removes the first sacrificial material without materially etching the second and third semiconductor sublayers in each active strip or the second sacrificial material and wherein the removing forms recesses or cavities between the second and third layers of semiconductor

101 sublayers in each active strip.

59. The process of claim 58, further comprising depositing the first semiconductor sublayer of a second conductivity type into the recesses or cavities and conformal with the sidewalls of the second set of trenches, and then removing the first semiconductor sublayer from the sidewalls except from inside the recesses or cavities.

60. The process of claim 59, further comprising forming a charge- storage layer conformal with the sidewalls and extending over the bottom of each of first set of trenches exposed by removing the second sacrificial material.

61. The process of claim 60, wherein the charge- storage layer comprises a tunnel dielectric film of 1-8 nm thick that is formed by chemical or atomic layer deposition, or oxidation of silicon oxide, or oxidation of silicon nitride, or a band gap-engineered oxide- nitride- oxide dielectric sandwich, the process further comprising depositing a charge trapping layer including silicon rich silicon nitride of 4-8 nm thickness, capped with a 4-15 nm blocking dielectric film selected from silicon oxide, or a high dielectric constant film of materials including aluminum oxide, hafnium oxide or some combination thereof.

62. The process of claim 61, further comprising: providing in the first set of trenches a conductive material adjacent the exposed charge- storage layer; and patterning and etching the conductive material to form a plurality of conductors that extend lengthwise along a third direction that is substantially perpendicular to the surface of the semiconductor substrate.

63. The process of claim 62, further comprising: providing a dielectric layer over the stacks of active strips and the conductors; forming openings in the dielectric for electrically contacting the conductors in the first set of trenches; and

102 providing a second set of low resistivity conductor wirings over the dielectric layers, the second set of low resistivity conductor wirings making electrical contact with the conductors through the openings in the dielectric layer.

64. The process of claim 63, wherein the second or the third semiconductor sublayer of each active strip is connected to the second set of low resistivity conductor wirings through the openings in the dielectric layer provided as a set of stepped staircase vias.

65. The process of claim 64, further comprising, prior to providing in the first set of trenches the conductive material, removing the charge- storing layer from at least each alternate bottom of the first set of trenches to expose openings for electrical contact to the first set of low resistivity conductor wirings, and wherein the openings in the dielectric layer to the second set of low resistivity conductor wirings is provided only to conductors without electrical contacts to the first set of low resistivity wirings.

66. The process of claim 61, wherein only sidewalls in selected ones of the first set of trenches are provided the charge- storage layer, and wherein removing the first sacrificial material is performed after the charge- storage layer is formed, such that sidewalls not covered by the charge- storage layer provide back-side access to removing the first sacrificial material.

67.. The process of claim 57, further comprising: controlled sideway etching to remove at least a portion of the first sacrificial material to form recesses in sidewalls of each stack of active strips, such that recesses from opposite sides of each active strip are separated from each other by the remainder of the first sacrificial material in the active strip; and depositing semiconductor material of a second conductivity type to form a first semiconductor sublayer in the recesses and conformal over the sidewalls of the stacks of active strips.

68. The process of claim 67, further comprising, prior to depositing the semiconductor

103 material, providing a dopant diffusion-blocking layer conformal with the recesses by chemical or atomic layer deposition or by thermal growth, the diffusion-blocking layer having a thickness between one atomic layer and three nanometers.

69. The process of claim 52, further comprising providing in each plane of semiconductor material a low resistivity metallic or silicide sublayer that is in contact with one or both of the second and third semiconductor sublayers.

70. The process of claim 62, further comprising removing at least a portion of the charge- storage layer along the sidewalls of the stack of active strips in areas located between conductors.

71. The process of claim 52, wherein the second and third semiconductor sublayers of a first conductivity type is provided by: providing layers of a third sacrificial material to sandwich the first sacrificial layer; selectively removing the third sacrificial material to form cavities; and filing the cavities with semiconductor material to simultaneously form the second and third semiconductor sublayers of the stack.

72. The process of claim 68, further comprising: providing, in each plane of semiconductor material, a fourth sacrificial layer between the second or third semiconductor sublayer and an adjacent one of the isolation layers; selectively removing the fourth sacrificial layers to form recesses or cavities; filling the cavities with a low resistivity metallic or silicide sublayer that contacts the second or the third semiconductor sublayer; and

104 removing the low resistivity metallic or silicide sublayer from the side edges of each active strip.

73. A semiconductor manufacturing process for three-dimensional memory blocks, comprising: providing a semiconductor substrate and forming circuitry therein and thereon; forming a first set of low resistivity conductor wirings above the semiconductor substrate and connected to the circuitry through via openings; depositing and planarizing a first isolation layer; forming a first set of buried contacts in the first isolation layer to provide electrical connections to the circuitry in the semiconductor substrate; forming over the first isolation layer a first plane of semiconductor material, the first plane of semiconductor material comprising a layer of a first sacrificial material defining a space for a first semiconductor sublayer to be formed, and second and third semiconductor sublayers of a first conductivity type separated by the layer of the first sacrificial material, wherein the first set of buried contacts provide electrical contact between the second or the third semiconductor sublayers and the circuitry in the semiconductor substrate; patterning and removing portions of the first plane of semiconductor material to make room for a next set of buried contacts; repeating for a predetermined number of times the steps of (i) depositing an additional isolation layer; (ii) forming the next set of buried contacts to provide electrical connections to the circuitry in the semiconductor substrate; (iii) forming over the additional isolation layer an additional plane of semiconductor material, comprising a layer of the first sacrificial material, and second and third semiconductor sublayers of the first conductivity type separated by the layer of the first sacrificial material, wherein one

105 or more of the second and third semiconductor sublayers of the additional plane of semiconductor are electrically contacted by one of that next set of buried contacts; and (iv) patterning and removing portions of the additional plane of semiconductor material to provide room for an additional next set of the buried contacts; and patterning and anisotropically etching the isolation layers and the planes of semiconductor material to form an array of active strips, the array of active strips comprising a plurality of stacks of active strips separated from each other along a first direction by a first set of trenches having sidewalls running lengthwise along a second direction that is substantially parallel to a surface of the semiconductor substrate; forming a charge- storage layer conformal with the exposed sidewalls of the stacks of active strips; patterning and etching openings in the charge- storage layer to expose areas in one or both the sidewalls of each stack of active strips; selectively etching the first sacrificial material in each active strip from the exposed sidewalls to form one or more cavities between the second and third

semiconductor sublayers; and depositing semiconductor material in the cavities and in selected portions of the exposed ones of the first set of trenches to form a first semiconductor sublayer and pillars of semiconductor material in the exposed ones of the first set of trenches.

74. The process of claim 73, wherein the isolation layers separating adjacent planes of semiconductor materials are etched to create air gaps that lessen parasitic capacitive coupling between the active strips.

75. The process of claim 73, wherein the pillars of semiconductor material partially wrap around the active strips in each stack to electrically shield between proximate active strips.

76. The process of claim 75, wherein the pillars of semiconductor material connect the

106 first sublayers of each active strip to circuitry in the semiconductor substrate.

77. A method for a system controller or a host device to rapidly determine the location of the most current version of a data file stored on one of many memory circuits, comprising: in each memory circuit:

(a) associating a designated one or more pages of the data file with a unique identifier index number generated by the system controller and appending the unique identifier index number to the data file; and

(b) associating a time-stamp with the unique identifier index number every time the data file is stored or updated in the memory circuit, wherein all unique identifier index numbers for all files stored in each memory circuit are stored in a lookup table in the memory circuit with the latest time- stamp and the location in the memory circuit at which the file is stored; sending from the system controller or the host device a search request which is broadcast simultaneously to one or more of the memory circuits, the search request specifying the unique identifier index number of the file to be located; and in each memory circuit, using exclusive-or (XOR) circuits or content addressable memory (CAM) circuits to compare the broadcasted unique identifier index number with the unique identifier index numbers stored in the look-up table of the memory circuit and reporting to the system controller when a match has been found along with its time- stamp and location, wherein when more than one match is found, the system controller selects from the reported locations the location whose associated time-stamp is the latest among the time-stamps reported.

78. The method of claim 77, wherein each memory circuit comprises a portion which is configured to operate as a low read-latency cache memory, and wherein the look-up table is stored in the cache memory.

107

79. The method of claim 77, wherein each memory circuit comprises a data integrity circuit which, upon detecting an error in the memory circuit, communicates the error to an on- chip error-correcting circuitry or to the system controller, thereby enabling the on-chip error- correcting circuitry or the system controller to carry out a data recovery and program-refresh operation.

80. The method of claim 77, wherein each memory circuit comprises an interface circuit that allows direct access to the memory circuit using one or more conventional DRAM, SRAM, NOR flash, NAND flash, Flash solid state drive, word- wide or serial bit steaming protocols.

81. The method of claim 77, further comprising, in each memory circuit, performing a read-refresh or program-refresh operation on a portion of the memory circuit in a background mode, while carrying out concurrently read, program, or erase operations in a second portion of the memory circuit and powering down a third portion of the memory circuit.

82. The method of claim 77, further comprising storing on-chip resource management data in each memory circuit, the on-chip resource management data includes one or more of: an updatable file allocation table for files stored in the memory circuit, a unique identifier index number, a program/erase cycle count, chip temperature, and a time- stamp that is appended to each stored data file when it is updated.

83. The method of claim 77, further comprising providing, in each memory circuit, a pipeline streaming circuitry that overlaps sensing a memory page of stored data in sense amplifiers and transferring the sensed data to a data buffer for serial bit stream, or parallel word- wide output from the memory circuit, with concurrently reading a next memory page of the stored data from the memory structure for sensing in the sense amplifies.

84. A memory circuit organized into a plurality of memory pages, comprising control circuitry for (a) associating a designated one or more memory pages to a data file and associating with the data file a unique identifier index number generated by a system controller or a host device; and associating a time- stamp with the unique identifier index number every time the data

108 file is stored or updated in the memory circuit, wherein all unique identifier index numbers for all files stored in the memory circuit are stored in a lookup table in the memory circuit with the latest time- stamp and the location in the memory circuit at which the file is stored.

85 The memory circuit of Claim 84, wherein the control circuitry comprises exclusive-or (XOR) circuits or content addressable memory (CAM) circuits for comparing a unique identifier index number of a data file to be located sent from the system controller with the unique identifier index numbers stored in the look-up table and wherein the control circuitry reports to the system controller or the host device when a match is found, sending along a time- stamp and a location of the data file found matching.

86. The memory circuit of claim 84, wherein the memory circuit further comprises a portion which is configured to operate as a low read-latency cache memory, and wherein the look-up table is stored in the cache memory.

87. The memory circuit of claim 84, wherein the memory circuit further comprises a data integrity circuit which, upon detecting an error in the memory circuit, communicates the error to an on-chip error-correcting circuitry or to the system controller, thereby enabling the on- chip error-correcting circuitry or the system controller to carry out a data recovery and program- refresh operation.

88. The memory circuit of claim 84, further comprising circuitry for concurrently carrying out (i) a read-refresh or program-refresh operation on a portion of the memory circuit in a background mode, (ii) read, program, or erase operations in a second portion of the memory circuit and (iii) powering down a third portion of the memory circuit.

89. The memory circuit of claim 84, further comprising storage for on-chip resource management data, the on-chip resource management data includes one or more of: an updatable file allocation table for files stored in the memory circuit, a unique identifier index number, a program/erase cycle count, chip temperature, and a time- stamp that is appended to each stored data file when it is updated.

109

90. The memory circuit of claim 84, further comprising pipeline streaming circuitry that overlaps sensing a memory page of stored data in sense amplifiers and transferring the sensed data to a data buffer for serial bit stream, or parallel word-wide output from the memory circuit, with concurrently reading a next memory page of the stored data from the memory structure for sensing in the sense amplifies.

110