Title:
ISO/NESTED CASCADING TRIM CONTROL WITH MODEL FEEDBACK UPDATES
Document Type and Number:
WIPO Patent Application WO2006036245
Kind Code:
A3
Abstract:
This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
Inventors:
YAMASHITA ASAO (US)
FUNK MERRITT LANE (US)
PRAGER DANIEL (US)
FUNK MERRITT LANE (US)
PRAGER DANIEL (US)
Application Number:
PCT/US2005/023580
Publication Date:
September 08, 2006
Filing Date:
June 30, 2005
Export Citation:
Assignee:
TOKYO ELECTRON LTD (JP)
YAMASHITA ASAO (US)
FUNK MERRITT LANE (US)
PRAGER DANIEL (US)
YAMASHITA ASAO (US)
FUNK MERRITT LANE (US)
PRAGER DANIEL (US)
International Classes:
H01L21/66
Foreign References:
| US20030228532A1 | 2003-12-11 | |||
| US6297166B1 | 2001-10-02 | |||
| US20010031506A1 | 2001-10-18 |
Other References:
NAGASE M ET AL: "Accurate gate cd control for 130nm cmos technology node", 2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING. CONFERENCE PROCEEDINGS. ( ISSM 2003 ). SAN JOSE, CA, SEPT. 30 - OCT. 2, 2003, IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, NEW YORK, NY : IEEE, US, 30 September 2003 (2003-09-30), pages 183 - 186, XP010667431, ISBN: 0-7803-7894-6
NAGASE M ET AL: "ADVANCED GATE ETCHING FOR ACCURATE CD CONTROL FOR 130-NM NODE ASIC MANUFACTURING", IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 17, no. 3, August 2004 (2004-08-01), pages 281 - 285, XP001200851, ISSN: 0894-6507
NATZLE W C ET AL: "Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic", ADVANCED SEMICONDUCTOR MANUFACTURING, 2004. ASMC '04. IEEE CONFERENCE AND WORKSHOP BOSTON, MA, USA 4-6 MAY 2004, PISCATAWAY, NJ, USA,IEEE, US, 4 May 2004 (2004-05-04), pages 61 - 65, XP010768964, ISBN: 0-7803-8312-5
TAJIMA M ET AL: "Advanced process control for 40nm gate fabrication", 2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING. CONFERENCE PROCEEDINGS. ( ISSM 2003 ). SAN JOSE, CA, SEPT. 30 - OCT. 2, 2003, IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, NEW YORK, NY : IEEE, US, 30 September 2003 (2003-09-30), pages 115 - 118, XP010667415, ISBN: 0-7803-7894-6
NAGASE M ET AL: "ADVANCED GATE ETCHING FOR ACCURATE CD CONTROL FOR 130-NM NODE ASIC MANUFACTURING", IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 17, no. 3, August 2004 (2004-08-01), pages 281 - 285, XP001200851, ISSN: 0894-6507
NATZLE W C ET AL: "Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic", ADVANCED SEMICONDUCTOR MANUFACTURING, 2004. ASMC '04. IEEE CONFERENCE AND WORKSHOP BOSTON, MA, USA 4-6 MAY 2004, PISCATAWAY, NJ, USA,IEEE, US, 4 May 2004 (2004-05-04), pages 61 - 65, XP010768964, ISBN: 0-7803-8312-5
TAJIMA M ET AL: "Advanced process control for 40nm gate fabrication", 2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING. CONFERENCE PROCEEDINGS. ( ISSM 2003 ). SAN JOSE, CA, SEPT. 30 - OCT. 2, 2003, IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, NEW YORK, NY : IEEE, US, 30 September 2003 (2003-09-30), pages 115 - 118, XP010667415, ISBN: 0-7803-7894-6
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