Title:
CHIP PACKAGING STRUCTURE AND PREPARATION METHOD
Document Type and Number:
WIPO Patent Application WO/2024/051237
Kind Code:
A1
Abstract:
Provided in the present invention are a chip packaging structure and a preparation method therefor. The packaging structure comprises a substrate, a first redistribution layer, first chips, virtual silicon wafers, a plastic packaging layer, a second redistribution layer, second chips, a metal connection through hole and a heat dissipation element. By means of introducing to two sides of the first chips virtual silicon wafers with a lower thermal expansion coefficient, mismatch of the thermal expansion coefficient of the packaging structure can be reduced, thereby reducing warpage of chips during a packaging process. By means of forming metal connecting columns between the first chips and the second chips, a heat dissipation channel is built, thereby further reducing packaging thermal resistance, and thus improving the heat dissipation efficiency of the chips. Thus, in combination with a heat dissipation element, a chip packaging structure with better heat dissipation performance is formed.
Inventors:
CHEN YENHENG (CN)
LIN CHENGCHUNG (CN)
YANG JIN (CN)
LIN CHENGCHUNG (CN)
YANG JIN (CN)
Application Number:
PCT/CN2023/099209
Publication Date:
March 14, 2024
Filing Date:
June 08, 2023
Export Citation:
Assignee:
SJ SEMICONDUCTOR JIANGYIN CORP (CN)
International Classes:
H01L21/50; H01L21/56; H01L23/31; H01L23/367; H01L23/373
Foreign References:
| CN114188225A | 2022-03-15 | |||
| CN107527880A | 2017-12-29 | |||
| CN115692222A | 2023-02-03 | |||
| CN114975409A | 2022-08-30 |
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (GENERAL PARTNERSHIP) (CN)
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