BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to latch devices. More particularly, it relates to a method of improving the metastable resolving time in binary or two state latch devices.

2. Prior art

In practice, metastability is where a bistable element such as, for example, a latch device or flip-flop, requires an indeterminate amount of time to generate a valid output. This phenomenon occurs in systems where the input data changes randomly with respect to the system clock. In other words, it is an attempt to synchronize the system clock with an asynchronous input. The time it takes for the device to resolve to stable state depends on the metastability time-constant tau (T). Tau is the primary term used to determine the MTBF, or Mean Time Between Failure. Another term used in this determination is T ₀ (T zero). These parameters are generally empirically measured by performing bench tests of the device, and arriving at a suitable curve for clock-to-output delays versus frequency-of-occurrence.

Prior research and studies have determined that the tau (T) of the circuit is inversely proportional to the transconductance (g,„) of the transistors in the latch circuit which is in the metastable state. Tau ultimately represents "how hard" the circuit is trying to resolve to one of the two stable operating states. As would be expected, much of this depends on technology, for example, the parasitic capacitances in the circuit, the gate lengths of the transistors, etc. "How hard" also means "how much energy is being expended" trying to resolve to one of the two stable operating states. This is reflected in a power-supply related term for tau. Thus, there is a dependence on MOS transistors thresholds for CMOS circuits of the form:

Tau - Constant / (V, _uppl> . - (2) (V ) ⁿ

Where: V, _upplv = Supply voltage to the latch circuit n = an exponential factor between 1 and 2

V _Λ = the threshold voltage of a MOS-transistor.

Since V^ is in the range of 0.7 - 1.0 volts for both n-channel and p-channel MOS transistors, "tau" increases dramatically as V, _upplv lowers towards (2 x W^). Since tau is the exponent term of the MTBF, it becomes clear that the MTBF increases radically as system supply voltages approach 1.5 - 2 volts. Previous, unsuccessful attempts for improvement of latch metastable resolution have involved detection and then transfer of the decision to yet another latch. These solutions have failed because they simply transfer the problem from one location to another. In this way, the second latch could have the same or other metastability problems.

The present invention addresses the problem of resolving time in latch devices, and shows that the metastable condition can be detected and the circuitry can be changed such that the time needed to resolve to a stable state (i.e. , tau) can be significantly reduced, thereby minimizing the MTBF.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a method and circuit for improving metastable resolving time in low power integrated circuits that detects a metastable condition in latch devices.

It is another object of the invention to provide a method and circuit for improving metastable resolving time in low power integrated circuits that locally increases power to the decision making circuit upon detection of the metastable condition.

Yet another object of the invention is to provide a method and circuit for improving metastable resolving time in low power integrated circuits that applies a localized power increase to the decision making circuit without increasing the power consumed by the remaining portions of the circuit.

It is a further object of the invention to provide a method of improving metastable resolving time in low power integrated circuits that operates efficiently and reliably.

The present invention provides a method and circuit for improving the metastable resolving time in low power integrated circuits. According to the invention, the metastable state of any latch device is detected through circuitry, and a localized increase in power-supply voltage is applied to the decision making circuit. The localized increase in power to the decision making circuit (i.e. , latch device) causes the circuit to resolve to a

stable operating state faster, and thus reduces the resolving time constant tau of the decision network.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and features of the present invention will become apparent from the following detailed description considered in connection with the accompanying drawings which disclose several embodiments of the present invention. It should be understood, however, that the drawings are designed for the purpose of illustration only and not as a definition of the limits of the invention.

FIG. 1 is a circuit block diagram of the method of improving metastable resolving time according to the invention;

FIG. 2 is a schematic circuit diagram of a first embodiment of the invention; and FIG. 3 is a schematic circuit diagram of a second embodiment of the invention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

FIG. 1 shows a block diagram of a binary, or 2-state latch 10 having a difference detector 12 coupled to the outputs. Difference detector 12 has an output that is feedback to the binary latch 10. When the difference detector 12 detects a metastable condition in latch 10, detector 12 provides localized power to the latch 10. The application of localized energy to the decision making circuit causes that circuit to resolve to a stable operating state more rapidly than it would under ordinary operating conditions. This concept applies to any physical multi-state memory element or device.

FIG. 2 shows the first embodiment of the invention, or a BiCMOS circuit version of the invention. This is a direct application of the "more energy" theory, that is, detecting the metastable condition, and locally applying more energy to the decision making circuit of the latch 10. The transconductance g _m of a bipolar transistor is linearly dependent on the collector current Ic. g, = die / dVbe « Ic The resolving time constant tau r is reduced when the gain, or transconductance g _m , is increased. Referring to FIG. 2, Bipolar NPN transistors Q l and Q2 form a cross- coupled latch through resistors R3 and R4, and the supply current is coupled through

resistors RI and R2. The values of RI and R2 are high enough to maintain the normal operating current of the latch low. During either of the normal states of the latch, transistors Q3 and Q4 are off, so that no current conducts through resistors R5 and R6.

During the normal state of the circuit, either one of the transistors Ql or Q2 is on, and the other is off. Assuming Ql is off (i.e. , conducting zero current), the voltage at node A will be determined by the resistor divider R1/R3, with the bottom node of resistor R3 at the Vbe voltage of on-transistor Q2 (i.e., approximately 0.8 volts). Resistor R3 should be significantly larger than resistor RI . Thus, assuming a 10: 1 ratio (e.g., RI is Ik ohms, R3 is 10k), the voltage VA at resistor RI is:

( ( V _cc -0 . 8 ) * 10k)

VA = + 0 . 8 = 4 . 62 vol ts ( li +l Or )

(assuming V _cc = 5 volts)

The voltage VB at node B will be determined by the saturation voltage of on transistor Q2, approximately 0.2 volts. N-channel MOS transistors Q5 and Q6, along with P-channel MOS transistors

Q7 and Q8, form a 2-input CMOS NOR gate. The effect of node A being a "high" (4.62 volts) causes the NOR gate output voltage C to be low (0 volts), thus turning off bipolar NPN transistors Q3 and Q4. In this case, no current can flow through resistors R5 and R6. If the latch (i.e. formed by Ql and Q2 through R3 and R4), becomes metastable, both transistors Ql and Q2 are 'on' in the active (non-saturated) region. The base nodes of Ql and Q2 will both be at 0.8 volts. The current through resistors R3 and R4 will be very low, supplying only the current needed by the transistors in their active state (this is typically 1/100th of the collector current). Since resistors R3 and R4 are, in this example, 10 times the value of resistors RI and R2, the voltage across resistors R3 and R4 will be approximately 1/10th the voltage across resistors RI and R2, or approximately 0.4 volts. Thus, the voltage at nodes A and B will be approximately 1.2 volts (0.8 plus 0.4) when the latch is in the metastable region.

These values of voltages VA and VB (approximately 1.2 volts) will be logic "low" inputs to the CMOS NOR gate, which has an input threshold of approximately 1/2 V _cc . Thus, the output C will go high (i.e. , to V _L ) turning on transistors Q3 and Q4. This will cause current flow through resistors R5 and R6, which are connected to the latch output

nodes A and B. This additional current flow increases the energy in the latch and decreases the metastable resolving time. The additional current consumption occurs only in a transient fashion, being removed once either node A or B goes high (causing NOR gate output C to return to a low state). FIG. 3 shows a second embodiment of the invention. Transistors Q1/Q3 and

Q2/Q4 form two back-to-back inverters, creating a binary latch with outputs A and B.

Transistor Q5 has a "set" signal attached to its gate, causing node A to go low when the "set" signal goes high. If node A is initially high, and the "set" signal goes high for a very short duration, node A starts to go low, and causes node B to start to go high through the action of the inverter formed by Q2/Q4. It is then possible for node A and node B to be equal at the point the "set" signal goes back low, causing the latch to go into the metastable state.

The exclusive-OR gate 14 has as its inputs node A and B. The output node C is high only if node A and node B are logically different (i.e. , one is high and the other is low). This is normally the case, and p-channel transistors Q7 and Q8 will be off (i.e., non¬ conducting).

In the metastable state, however, nodes A and B will be the same logical levels, causing Ex-Or gate output node C to go low. This turns on transistors Q7 and Q8 fully (their gate voltages, which are connected to node C, are at ground potential). This contrasts to the other P-channel transistors Q3 and Q4 which have their gate voltages sitting at half¬ way between V _ce and ground, thus having much reduced current.

The increased currents from Q7 and Q8 are fed into the latch output nodes A and B, causing the gate voltages of Ql and Q2 (which are connected to these nodes) to rise. The higher gate voltages cause Ql and Q2 to conduct more current (taking the current from Q7 and Q8). This higher-voltage, higher current operating point results in higher transconductance (higher gain) for these transistors Ql , Q2, thus increasing the speed at which the latch resolves itself, and thereby lowering tau.

Note that the higher voltages A and B effectively turn off transistors Q3 and Q4, the p-channel transistors in the CMOS inverters. Transistors Q7 and Q8 act, in this case, as passive (resistor-type) loads, reducing the effective number of MOS transistors in series between V _cc and ground from two to one (CMOS case).

When the latch finishes its resolution, nodes A and B become logically different, causing node C to return to a high level, shutting off transistors Q7 and Q8. The circuit returns to its zero-supply-current CMOS operation.

While several embodiments of the present invention have been shown and described, it is to be understood that many changes and modifications may be made thereunto without departing from the spirit and scope of the invention as defined in the appended claims.